IMX8QM hardware design LPDDR4

[timur_kh]

Hello everyone!
The schematic of IMX8QM (SPF-29420_C5) on pages 14-15 shows an example of an LPDDR4 connection. Do I understand correctly that the DDR_CH[1:0].DQ_[15:0] and DR_CH[1:0].DQ_[31:16] ports can be connected depending on the footprint (simplify PCB design)? If Yes, then this is configure in the Config Tools for i.MX v8?

Second question. In the diagram on page 15, the names of the LPDDR4 channels do not match, i.e. the MX8QP channel A is connected to the LPDDR4 channel B and vice versa, this is also done to simplify the design of the PCB?

Third question. In my device there is DR_CS 1_CS 0_A, but there is no DDR_CH1_CH1_A. How do I properly connect DDR_CS1_CS0_A?

[timur_kh]

Oh, I made a typo.
Please look at the attached picture.

[igorpadykov]

so what ddr part used in the case, in general in each lpddr4 datasheet section

"Package Block Diagrams" one can find recommended connections.

So if there are no CKE1, CS1 seems this is single rank part, use only CKE0, CS0.

Best regards
igor

[igorpadykov · Accepted solution]

Hi timur_kh

> Do I understand correctly that the DDR_CH[1:0].DQ_[15:0] and DR_CH[1:0].DQ_[31:16] ports

>can be connected depending on the footprint (simplify PCB design)?

yes

>Second question. In the diagram on page 15, the names of the LPDDR4 channels do not match, i.e. the >MX8QP channel A is connected to the LPDDR4 channel B and vice versa, this is also done to simplify the >design of the PCB?

yes

>Third question. In my device there is DR_CS 1_CS 0_A, but there is no DDR_CH1_CH1_A.

>How do I properly connect DDR_CS1_CS0_A?

what do you mean exactly, in SPF-29420_C5 there is also no DDR_CH1_CH1_A.

Best regards
igor