IMX8QM/8QP MIPI-CSI2 max resolution

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IMX8QM/8QP MIPI-CSI2 max resolution

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takayuki_ishii
Contributor IV

Hello community,

 

 

Some community thread were talk about iMX8QM ISI errata

ERR050066: ISI: Data overflows occur when input streams exceed AXI transaction frequency

like this.

8 x 1080p MIPI CSI2 cameras capture in iMX8QM 

 

In this errata

"However, combinations of sensors which add

up to less than 2Mpixel are supported with current design."

mean that

1) 2Mpixel mean that 1920x1080 = 2,073,600 is correct?

2) How about frame rate.1920x1080 @60 or 1920x1080 @30

 

Does this apply to each channel individually?

Can it capture for 2ch 1920x1080 @60 support?

MIPI-CSI2_01920 x 1080 @60
MIPI-CSI2_11920 x 1080 @60

 

The other hand, i.MX8QXP_C0 silicon have no errata "ERR050066: ISI: Data overflows occur when input streams exceed AXI transaction frequency"..

Is it support 4K@30 video capture?

devicechresolutionfps
i.MX8QM21920x108060
i.MX8QP21920x1080

60

i.MX8QXP13840x216030

 

Best regards,

Ishii

 

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joanxie
NXP TechSupport
NXP TechSupport

the mipi csi capture max is 6Gbps, so should can support 4k, but we didn't test this, maybe would have issue when capture 4k, only test resolution is 1280x800@30, we didn't test 6Gbps, I think 6Gbps maybe cause some bandwidth issue, I only can say we tested max thoughout is 4x1280x800@30

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sbertrand
Contributor III

I would like to follow up on the iMX8QM CSI2 Bandwidth.

In the TRM I have the following information about the clocks used in CSI-2 module.

With a single pixel interface, data_out contains a single pixel every clock that dav_out
(data valid) is asserted. The single pixel interface must run at a frequency that is equal to
number of MIPI lanes times the byte lane frequency.

clk :
RX Controller Core Clock input. This clock must be exactly equal to or faster than the receive byteclock, RxByteClkHS_ln0, from the RX DPHY.

clk: SSSLICE2 : LPCG_MIPI_CSI_LPCG_24

clk_ui:
User interface clock. The frequency of clk_ui must be such that the data received on the data_out output is greater than or equal to the total bandwidth of the physical MIPI interface. Clk_ui has no relationship requirement with regards to ‘clk’ other than the bandwidth requirement mentioned previously.

clk_ui: SSSLICE2: LPCG_MIPI_CSI_LPCG_24

From the clock subsystem, CLK and CLK_UI have the same frequency.

Can the CSI-2 block process all the data when all 4 lanes are receiving at 1.5Gbps ?

clk is generated from DIG_PLL0 @ 720 MHZ, a divider provides 360MHz. Can clk be provided a higher frequency ?

Based on the TRM : clk >= lanes * mipi_lane_freq*DDR / 8 >= 4*2/8 * mipi_lane_freq.
Am I correct to add all the lanes byteclock for the overall receive byteclock ?

Is there a bandwidth limitation at the CSI-2 level ?

CSI-2 6Gbps would need 16.666 x 360MHz. I am not sure of the internal bus width that processes the Rx DPHY data.

 

 

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takayuki_ishii
Contributor IV

Hello community.

 

Don't you have any update?

 

Best regards,

Ishii.

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joanxie
NXP TechSupport
NXP TechSupport

for ERR050066 , this issue is fixed in imx8qxp C0, for imx8qm, can support 4k@30 on theory, but we don't tested this, only tested 4x1280*800@30Hz successfully, so for 4k@30, if  system loading is heavy, there is something wrong with capture

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takayuki_ishii
Contributor IV

Hello @joanxie 

 

Thank you for your reply.

We will reply to the customer that max capture size of i.MX8QM is 4K@30 are the official specifications.

 

Is it correct in my understanding that it works at 4k@30 per channel for MIPI-CSI2?

 

Best regards,

Ishii.

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joanxie
NXP TechSupport
NXP TechSupport

yes, each mipi csi port has this performance

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takayuki_ishii
Contributor IV

Hello @joanxie 

 

Thank you for your reply.


How about color format of tested capture 4x1280*800@30Hz.

It is boundary of ISI limitation.

4x1280*800@30Hz*3Byte(RGB24bit) > 2Mpixel(ISI limit) > 4x1280*800@30Hz*2Byte(YUYV16bit)

 

Best regards,

Ishii.

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joanxie
NXP TechSupport
NXP TechSupport

only tested YUYV16bit

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joanxie
NXP TechSupport
NXP TechSupport

only tested YUYV16bit

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joanxie
NXP TechSupport
NXP TechSupport

only tested YUYV16bit

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takayuki_ishii
Contributor IV

Hello @joanxie 

 

Thank you for your reply.

You say that "only tested 4x1280*800@30Hz successfully, so for 4k@30,"

 

I understand that only tested 4x1280*800@30Hz successfully,

throughput of this condition is lager than 2Gbps, so iMX8QM capture can support more than 2Gbps.

That is, the ISI limit is not affected, so the maximum supported size is 4K@30.

 

But if test condition is 4x1280*800@30Hz x 16bit/pixel,

This explanation is not valid. Because throughput of test condition is less than 2Gbps.

 

Which is correct?

1) Maximum capture size of iMX8QM is unknown.

2) It has no test but it supports 6Gbps, so it will be 4K@30.

 

Sorry to keep checking back, but we need accurate information on this specification

as it is an important issue that affects product planning.

 

Best regards,

Ishii.

 

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joanxie
NXP TechSupport
NXP TechSupport

the mipi csi capture max is 6Gbps, so should can support 4k, but we didn't test this, maybe would have issue when capture 4k, only test resolution is 1280x800@30, we didn't test 6Gbps, I think 6Gbps maybe cause some bandwidth issue, I only can say we tested max thoughout is 4x1280x800@30

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takayuki_ishii
Contributor IV

Hello @joanxie 

 

Thank you for your reply.

I understand that ISI errata050066 does not affect the capture performance of MIPI-CSI2, so MIPI-CSI2 capture max is 6Gbps and it should can support 4k.

Best regards,

Ishii.

 

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takayuki_ishii
Contributor IV

Hello @joanxie 

 

Please teach me a byte/pixel size of capture test for 4x 1280*800@30Hz

If it is 2byte/pixel = YUYV, the data volume for this test is less than 2 Gbps.

 

4x 1280`800 * 30 * 2byte/pixel = 1.966Gbps

 

This result does not prove that 4K capture is possible because it falls within the errata constraints.

I would appreciate your immediate attention to this matter.

 

Best regards,

Ishii.

 

 

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joanxie
NXP TechSupport
NXP TechSupport

for mipi csi of imx8qxp or imx8qm, which can supports up to 6Gbps, so can support 4k@30 or 1080p@60

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takayuki_ishii
Contributor IV

Hello @joanxie 

 

Thank you for your reply.

 

In Figure 15-1. Interconnection Diagram of Reference Manual IMX8QMRM Rev. 0,

MIPI-CSI2 connect to ISI.

So, MIPI-CSI2 can supports 6Gbps so it can capture 4K@30, 

Bat ISI have performance limitation 2MPixel.

I think that it is ok to use i.MX8QXP_C0 silicon because it is fixed this limitation.

But i.MX8QM have no C0 revision.

 

Is it can really capture 4K@30? to frame memory on DDR?

 

Best regards,.

Ishii.

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takayuki_ishii
Contributor IV

Dear community,

 

My concern is if the errata ERR050066 will affect the capture with MIPI-CSI2.
If affected, I am concerned that the maximum capture size will be limited.

Please see attached document.

takayuki_ishii_2-1670406008739.png

Best regards,

Ishii.

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