IMX8MQ and OV2311 ErrSotSync errors after repeated stream on and stream off

[saideepak_r]

We have designed custom carrier board with IMX8MQ chip. In our design, we have connected two cameras with IMX8MQ and camera connected to both MIPI CSI1 port and MIPI CSI2 port in IMX8MQ.

Sensor : OV2311 - Output RAW 8bit Format - MIPI Interface

BSP Version : L4.14.78_1.0.0_MX8MQ BSP.

Issue Description:

In some of the carrier boards, we are not receiving any frames from camera after few stop and start stream call in application. This issue occurs only in few carrier board. The frames not received from MIPI CSI1 port in some boards and frames not received from MIPI CSI2 port in some boards but this issue is seen in both MIPI CSI port and it's not specific to specific port.

When issue occurs, The application just wait for frame buffer in dequeuebuffer IOCTL call and not faced "Base address switch error" or "Rxfifo overflow error" during the issue recreated. The sequence to recreated issue, call repeated stream on and stream off call 10 to 15 iteration then this issue will occur. The only way to recover from this issue, need to reboot the system.

Debugging Details:

1. Probed MIPI Signal of camera output to confirm whether camera outputs frames during the issue. It's confirmed that camera output frames but it's not sampled by IMX8MQ.
2. When the Issue occurs, not received any interrupt in "mx6s_csi_irq_handler" function of mx6s_capture.c. Not even SOT frame interrupt received during the issue
3. Register Dump of MIPI PHY is given below,

[ 766.856108] MIPI CSI2 HC num of lanes 0x100 = 0x1

[ 766.861446] MIPI CSI2 HC dis lanes 0x104 = 0xc

[ 766.866800] MIPI CSI2 HC BIT ERR 0x108 = 0x0

[ 766.871978] MIPI CSI2 HC IRQ STATUS 0x10C = 0x13d

[ 766.877320] MIPI CSI2 HC IRQ MASK 0x110 = 0x1ff

[ 766.882667] MIPI CSI2 HC ULPS STATUS 0x114 = 0x0

[ 766.887835] MIPI CSI2 HC DPHY ErrSotHS 0x118 = 0x0

[ 766.893054] MIPI CSI2 HC DPHY ErrSotSync 0x11c = 0x3

[ 766.898224] MIPI CSI2 HC DPHY ErrEsc 0x120 = 0x0

[ 766.903390] MIPI CSI2 HC DPHY ErrSyncEsc 0x124 = 0x0

[ 766.908556] MIPI CSI2 HC DPHY ErrControl 0x128 = 0x2

[ 766.913723] MIPI CSI2 HC DISABLE_PAYLOAD 0x12C = 0x0

[ 766.918941] MIPI CSI2 HC DISABLE_PAYLOAD 0x130 = 0x0

[ 766.924107] MIPI CSI2 HC IGNORE_VC 0x180 = 0x1

[ 766.929327] MIPI CSI2 HC VID_VC 0x184 = 0x1

[ 766.934493] MIPI CSI2 HC FIFO_SEND_LEVEL 0x188 = 0x40

[ 766.939799] MIPI CSI2 HC VID_VSYNC 0x18C = 0x0

[ 766.944978] MIPI CSI2 HC VID_SYNC_FP 0x190 = 0x0

[ 766.950198] MIPI CSI2 HC VID_HSYNC 0x194 = 0x0

[ 766.955365] MIPI CSI2 HC VID_HSYNC_BP 0x198 = 0x0

       4. Register Dump of CSI is given below,

[ 416.959424] CR1 - 0x11b0902

[ 416.962216] CR2 - 0xc0000000

[ 416.965213] CR3 - 0x10a0

[ 416.967863] CR18 - 0xd44ad030

[ 416.970829] CSI_STAT_FIFO - 0x0

[ 416.974087] CSI_RX_FIFO - 0xffffffff

[ 416.977777] CSI_RX_COUNT_REG - 0x9600

[ 416.981558] CSI_DMA_ST_ADD - 0x0

[ 416.984901] CSI_DMA_SIZE - 0x0

[ 416.988072] CSI_FRM_BUF - 0x0

[ 416.991037] CSI_IMG_PARAM - 0xc800514

[ 416.994815] CSI_ISR - 0x80204001

         5. Added sleep in stream on and stream off call. Also, during mipi_csi2_phy_reset() added delay. Nothing help out.

We suspect the MIPI CSI PHY not recovered from the state of ErrSotSync even the mipi_csi2_phy_reset() are handled during the stream on and stream off function call in mxc-mipi-csi2_yav.c file.

Also, we found similar issue already reported in NXP forum.

Link: https://community.nxp.com/t5/i-MX-Processors/IMX8-MQ-and-OV-5640-ErrSotSync-errors/m-p/1026822

As suggested in the above link, we tried to call mxc_mipi_csi2_phy_reset() in mxc-mipi-csi2_yav driver before v4l2_subdev_call streamoff and streamon functions call. It's seem like the PHY is not recovered from the ErrSotSync error once issue occurred.

Can you share us sample function definitions to write and read these registers,

setReg(0x30384650, 0);
setReg(0x30384660, 0);

Please help us on with your feedback on how to reset the MIPI PHY and recover from this error state to receive frames from camera without hard rebooting the system.

Please provide us valuable solution to fix this issue. We are in production phase and this issue is blocker for us in production.

Thanks for your help in advance.

Thanks,

Sai.

[jimmychan]

0x30384650 is the address of clock gating register CCM_CCGR101 which control the clock of MIPI CSI1. 0x30384660 is the address of clock gating register CCM_CCGR102 which control the clock of MIPI CSI2. Please refer to the Table 5-9 and the Chapter 5.1.7 CCM Memory Map/Register Definition for more details.

[jimmychan]

So, have you try to put the following in your ov2311 stream off function?

setReg(0x30384650, 0);
setReg(0x30384660, 0);

[saideepak_r]

Hi jimmychan,

I have tried using that clock registers in ov2311 stream off code but that issue didn't resolved.

The sequence that i tried is,

setReg(0x30384650, 0); //Turn off clock
setReg(0x30384660, 0); //Turn off clock

//delay

ov2311StreamOff();

setReg(0x30384650, 3); //Turn on clock
setReg(0x30384660, 3); //Turn on clock

//delay

ov2311StreamOn();

I also tried with adding some 20ms - 200ms delays between clock and stream on/off functions.  But still we face this issue.

Whether you have seen this issue before?

[jimmychan]

According to this link, the code is adding inside the stream off function.

static void OV5640_stream_off(struct ov5640 *sensor)
{
ov5640_write_reg(sensor, 0x4202, 0x0f); 
msleep(30);
setReg(0x30384650, 0);
setReg(0x30384660, 0);
ov5640_write_reg(sensor, 0x3008, 0x42);
}

According to the ov5640 datasheet, 0x4202 is the Frame Control register that the 0x0f is the Frame off number. And the 0x3008 is the System Control register that 0x42 is setting for the software power down.  So, you can try to modify the code of the function ov2311StreamOff().

[saideepak_r]

Hi,

We tried the suggested sequence in the driver code. Still we face the issue.

ErrSotSync is still set and it doesn't recovered.

Whether you have seen this issue before?

Please provide us valuable solution to fix this issue. We are in production phase and this issue is blocker for us in production.

[jimmychan]

Hello,

I got the reply from the internal team.

========================

1. "Base address switch error" ：

this may be related to sensor driver timing which is not good.

2. "Rxfifo overflow error" , this may be a band width issue.

what's the resolutions?   1080p ?

is the fifo overflow  always on MIPI CSI2?

=========================

Best regards,

Jimmy

[jimmychan]

what's the resolutions?   1080p ?

is the fifo overflow  always on MIPI CSI2?

=========================

Best regards,

Jimmy

[jimmychan]

I didn't see this issue before.

I will ask the internal team to see if any suggestion to debug this issue.

I will let you know when I get any update.