IMX8MP SDIO DDR50 clock issue

[vishal088]

Hello

We recently applied the following NXP fix from kernel v7.2-rc4.

58c08eea91572df62d71731f1d1180a0dc8e3a6f
mmc: sdhci-esdhc-imx: fix esdhc_change_pinstate() to allow default state restore

Before this fix, esdhc_change_pinstate() required all pin control state named default, state_100mhz and state_200mhz to be present in device tree before applying any timing-specific pin control state. Therefore, if any pin control was not defined in the USDHC device-tree node, the driver did not apply state_100mhz, even when the SDIO device switched to DDR50 timing.
With the fix, the driver validates and applies only the pin control state required for the selected timing mode. Therefore, state_100mhz is now correctly applied for SDR50 and DDR50 modes.

After applying this fix, we observed an issue with the SD2 clock-pad configuration in state_100mhz.

SDIO device (in DDR50 mode) does not work with:

MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194

However, SDIO device (in DDR50 mode) works with:

MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x184
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196

The 0x184 setting differs from 0x194 only in slew rate. The other working settings use different drive-strength values.

We understand this behavior may be related to signal integrity. However, the result is not straightforward: DDR50 fails with 0x194, but works both with a slower slew rate (0x184) and with a stronger drive setting (0x196).

In addition, SDR50 works correctly with 0x194. The issue is observed only in DDR50 mode.

Could you please advise whether there are other i.MX8MP USDHC/SDIO configuration requirements or known limitations that we should consider? We would also appreciate any recommended debugging steps.

Regards
Vishal

[vishal088]

Hi @Zhiming_Liu 

for state_100mhz SD2_DATA<X> is 0x194.

Regards
Vishal 

[Zhiming_Liu]

Hi @vishal088 

Can you also share the SD2_DATA<X> setting? 

Best Regards,
Zhiming