IMX8MP Problem with FPD Link III

[csander]

Hi there,

i have a problem regarding the connection between the IMX8MPLUS , the DS90UB947/8 SerDes and a 10 inch panel

My device tree is based off of a functioning variant, in which we didn't use the FPD Link and connected our panel directly to the LVDS signal from the IMX8MP.

I have explored almost every possible option there is and i really don't know any further.

The FPD Link is set up correctly: Single Link, OpenLDI Mapping, Single Pixel Input, Single Link Transport to Deserializer, Single Link JEIDA Output. Everything is 24 bit Video, I2C Passthrough is activated, the cable is set to STP on both devices, Port0 is selected on both devices, DE_GATE_RGB is activated.

The FPD Link is stable: Deserializer 0x1C[0,1] = 1, Serializer 0x0c[0,1,2] = 1

Looking at the 0x20 Register on the Serializer the functions of the Deserializer are correctly identified. 0x5A also shows that everything is supposed to be working fine [0,2,4,6,7] = 1, 0x5F also shows the correct pixelclock of 74,25MHz.

i am currently using this dts. 

Things i have tried: swapped data mapping of the lvds-channel and panel between jeida and spwg (all kinds of combinations), the timings are from another working dts, regarding the ldb i have tried adding either phys = <&ldb_phy> phy-names = "ldb_phy" as well as directly using ldb_phy1 neither worked, i have tried both lvds-channels either single or dual link.

I really dont know any further and would appreciate any kind of ideas you guys have.

[Zhiming_Liu]

Hi @csander 

Could you describe the current issue you meet in more detail? From your description, I can understand what you did, but I can't grasp the problem.

Best Regards,
Zhiming

[csander]

Ah yes of course, I wanted to edit the message afterwards to ad my actual problem but realised i couldn't edit it anymore.

First of all thank your for your fast reply.

My exact problem is the following:

I want to extend my video signaling via the FPD3Link and everything is wired up correctly but i can't get any image or video on my display.

When booting up my SoM and powering the display i can see that the backlight turns on but thats it.

And no matter what I do I can't get the lcd controller to connect with the ldb and I checked the manual to confirm that lcdif2 is for LVDS and at the address 32e9000

root@imx8mp-display:~# dmesg | grep -iE "lvds|ldb|lcdif|drm"
[ 0.051459] platform panel: Fixed dependency cycle(s) with /ldb-display-controller/lvds-channel@0
[ 1.422143] [drm] Initialized vivante 1.0.0 20170808 for 40000000.mix_gpu_ml on minor 0
[ 1.724239] imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops)
[ 1.732467] imx-drm display-subsystem: bound ldb-display-controller (ops imx8mp_ldb_ops)
[ 1.741177] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 1
[ 1.815820] imx-drm display-subsystem: [drm] fb0: imx-drmdrmfb frame buffer device
[ 1.823574] imx8mp-ldb ldb-display-controller: Failed to create device link (0x180) with 32e90000.lcd-controller
[ 4.082340] systemd[1]: Starting Load Kernel Module drm...

I have also tried watched the framebuffer change between values of 37 an 40
viawatch -n 0.5 "grep -nE 'plane\\[|fb=|crtc\\[33\\]|connector\\[35\\]' $STATE | head -n 60"
which indicates that some kind of visual is supposed to be seen.

I also edited the weston.ini to just show a one coloured background which did not do anything.

Killing weston and writing directly into the framebuffer also did not work.

[Zhiming_Liu]

Hi @csander 

If the hardware design is sound (this is crucial), the only remaining aspect to check at the software level is Pixel Polarity in static const struct display_timing-->flags and bus_flags.

Best Regards,
Zhiming