IMX8MP DDR Stress Tool Error

[abhiroopnray]

I am trying to boot a custom IMX8MP Board.

I have made the pin configuration changes in the LPDDR4_RPA excel file and trying to calibrate and run DDR Stress test using MScale DDR Tool.

I am getting the following:

1> When I click download with the .ds file:

Download is complete
Waiting for the target board boot...

===================hardware_init=====================

********Found PMIC PCA9450**********
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:52:12
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 2000MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 17, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 1
Density per chip select: 3072MB
Density per controller is: 6144MB
Total density detected on the board is: 6144MB
============================================

MX8M-plus: Cortex-A53 is found

*************************************************************************

2> When I press calibrate:

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @2000Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @200Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @50Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @2000Mhz...
[Process] End of initialization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Result] PASS

============ Step 2: DDR memory accessing... ============
Verifying DDR frequency [email protected]
Verifying DDR frequency [email protected]
Verifying DDR frequency [email protected]
[Result] OK

3> When I press Stress test with all default configuration: 

============ Step 3: DDR parameters processing... ============
[Result] Done

Success: DDR Calibration completed!!!
DDR Stress Test Iteration 1
--------------------------------
--Running DDR test on region 1--
--------------------------------

t0.1: data is addr test
...Address of failure: 0x0000000101E00000
Data read was: 0x0000FFFF41E0FFFF
But pattern was: 0x0000000041E00000

I am unsure about the error. Can anyone please tell me what this error is? Will the board be able to boot after this ?

[abhiroopnray]

Hello,

May I know, when can I get a response?

[Rita_Wang]

Did your board work well now? If no, you can share us your script and ddr section schematic to us, we will help check.

Wish you have a nice day

[abhiroopnray]

Hello,

Thank you for your response.

The board is working if I set the lpddr4 Clock frequency to 800MHz or 1200MHz. The above error persists when I set clock frequency to 2000MHz.

For 800MHz:

memory set

0x30360054

32

0x7D060

For 1200MHz:

memory set

0x30360054

32

0xC8022

For 2000MHz:

memory set

0x30360054

32

0xFA031

Can you please tell me do I need to make any other change for 2000MHz?