I found MIPI_DSI register description in imx8 m plus reference manual chapter 13.6.9.1, but no more details about these register setting. where can I get these setting details? For example, different value I set to M_THSPRPRCTL will cause what kind of result?
We don't have specific register information, even on MIPI D-PHY IP spec, Samsung doesn't describe them, for timing registers. Customers doesn't need calculate the timing by themselves this is defined on drivers.
Thanks. Our Data Lane HS-TX 20%-80% Rise/Fall Time is too slow in MIPI D-PHY SI test. Are there any resister setting can increase TX drive capacity or slew rate?
The register Master and Slave DPHY Control Low Register in chapter 13.2.3.1.10 of reference manual mentions HS-TX Rise and Fall Time Control bit field that could be helpful for you.
