IMX8M Mini: Configure SAI MCLK for 4.096MHz for 16Khz audio on upstream Linux

[timharvey]

Greetings,

I have a user with a need for native 16KHz audio streaming from an imx8mm SAI3 I2S to SGTL5000 codec. 

The SGTL5000 datasheet specifies that the MCLK must be an integer multiple of the sampling rate, typically 128x, 256x, 384x, or 512x the sampling rate (fs) with a max MCLK of 25MHz. For a 16kHz sampling rate the supported MCLK frequencies are:
- 2.048MHz (16kHz * 128)
- 4.096MHz (16kHz * 256)
- 6.144MHz (16kHz * 384)
- 8.192MHz (16kHz * 512)

The IMX8MM_AUDIO_PLL1_OUT is 786.432MHz which is an integer multiple of 24.576 MHz, suitable for 32Khz and 48kHz sampling rates IMX8MM_AUDIO_PLL2_OUT is 722.5344Mhz which is an integer multiple of 22.5792 MHz, suitable for 44.1 kHz sampling rates. These would need dividers in order to achieve 4.096MHz.

It looks like before the imx8mm clock driver was upstreamed to the Linux kernel there were options to divide it down but I don't see that in the upstream Linux kernel.

Is there any instructions on how to configure the SAI clock for a divided down rate of 4.096MHz?

[timharvey]

The solution you pointed to is using the downstream vendor kernel which has a IMX8MM_CLK_SAI1_DIV allowing IMX8MM_AUDIO_PLL1_OUT to be divided into additional frequencies - this is missing from the upstream Linux kernel and is what I'm asking about. Is there a way to divide this in the upstream kernel? I'm not that familiar with the Linux clock subsystem.

[Bio_TICFSL]

Hi,

I understand your use case, but unfortunately, the frequencies cannot be changed at run time from the software. The NXP does not provide support for the same. Changes in the device tree are recommended.

Regards

[Bio_TICFSL]

Hello,

one can look at solution provided in similar case

https://community.nxp.com/t5/i-MX-Processors/SAI-on-i-MX8M-Mini/m-p/959805

Also, please look at Chapter 16 Porting Audio Codecs https://www.nxp.com/docs/en/user-guide/UG10165.pdf

Regards