IMX8DXL PCIe Endpoint enumeration

[KK-SIE]

Hello Everyone,

It is related to PCIe link training + Enumeration.

Our setup:

Host: Intel with BIOS + Windows 10/Linux (debian) OS + PCIe Host

Device: imx8dxl PCIe Endpoint

I have imx8dxl configured as PCIe Endpoint. The link is up.

[   10.037555] pci_epf_test pci_epf_test.0: Failed to get private DMA rx channel. Falling back to generic one
[   10.037569] pci_epf_test pci_epf_test.0: Failed to get DMA channel
[   10.069805] imx6q-pcie 5f010000.pcie_ep: PCIe Gen.1 x1 link up
[   10.069841] imx6q-pcie 5f010000.pcie_ep: PCIe Gen.1 x1 link up
[   10.069855] imx6q-pcie 5f010000.pcie_ep: Link up, Gen1

Problem: imx8dxl PCIe endpoint device is not detected by Windows OS or Linux.

Questions:

1. What could be possible cause for not getting detected, inspite Link is Up?

2. As per PCIe Spec, after device power on + stable clock + PERST, we have 20 ms for Link training and 100ms for enumeration, is this correct? if so, how to achieve this with imx8dxl with uboot + Kernel which takes around 5 seconds for complete boot?

[KK-SIE · Accepted solution]

I got the document at the link: https://community.nxp.com/t5/P-Series/Configuring-PCIe-ports-in-endpoint-mode-in-uboot-and-Linux/m-p...

Answer: We need to do it in Uboot. Recommended to repartition the PCI Express initialization code and move it ahead of other code blocks irrelevant to PCI Express.

Snip:

Because a PCI Express endpoint card seated in each PCI Express slot of a x86 PC motherboard is only one of the many components that the entire PC system interoperates with, the system BIOS can not wait forever to discover the PCI Express endpoint card. To synchronize the PCI Express endpoint discovery process between the x86 PC host and the PCI Express endpoint card, the PCI Express CEM Specification defines a 100-msec rule from the de-assertion time of the PERST# (slot reset) to the time that a PCI Express root complex (host) is allowed to probe the connected downstream endpoint.

If a PCI Express endpoint card fails to respond the x86 PC host’s configuration cycle correctly at the time when the 100 msec expires, the host assumes it is malfunctioning. The x86 PC host BIOS might not wait for such PCI Express endpoint card to become available even the endpoint card might just need some more time to initialize itself. Such a PCI Express endpoint card would be disabled by the BIOS and become an undiscoverable PCI Express endpoint in the system.

....

In general, introducing less than a 10msec delay is fine. However, any delay beyond 10msec reduces the 100msec budget allocated from the slot reset’s deassertion to the configure cycle being responded by PCI Express end point. Therefore, it is recommended to repartition the PCI Express initialization code and move it ahead of other code blocks irrelevant to PCI Express.

[KK-SIE]

attached the document from the link

[KK-SIE]

Dear NXP Support team,

You expertise in this domain will be valuable direction to the project.

Kindly share you solutions. We look forward to your response.

Best regards,

KK