IMX8 mini UART4

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IMX8 mini UART4

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davidvescovi
Contributor IV

I have been trying to enable UART4 on our iMX8m Mini board.

I have read all the docs and reviewed other post concerning UART4 on the mini.

None help.

I would like to pin mux pad B8 and E6 which in the standard configuration are:

ECSPI2_MOSI and ECSPI2_SCLK to be used as UART4 TX and RX.

This looks like a valid configuration from all I have read.

I see the fsl-imx8mm.dtsi the following for UART4:

 uart4: serial@30a60000 {
  compatible = "fsl,imx8mq-uart",
        "fsl,imx6q-uart", "fsl,imx21-uart";
  reg = <0x0 0x30a60000 0x0 0x10000>;
  interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
   <&clk IMX8MM_CLK_UART4_ROOT>;
  clock-names = "ipg", "per";
  dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
  dma-names = "rx", "tx";
  status = "disabled";
 };

The compatible line seems to be in error so I changed it to:

  compatible = "fsl,imx8mm-uart",
        "fsl,imx6q-uart", "fsl,imx21-uart";

I then added the following to the &iomuxc in my .dts file:

pinctrl_uart4: uart4grp {
 fsl,pins = <
  MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX      0x00000116
  MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX      0x00000116
 >;
};

&uart4 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart4>;
 assigned-clocks = <&clk IMX8MM_CLK_UART4_SRC>;
 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
 status = "okay";
};

When I boot the kernel crashes with a panic.

If I go back and set status = "disabled" it boots but no UART4.

I suspect I missed some clock enable or something but I can't figure out what.

any help?

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8 Replies

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thiago_machado
Contributor III

Hello all,

I'd like to enable the UART4 for the IMX8M Nano, but I've not found yet no RDC Register configuration file in my build enviromentor. If the solution is to change the MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX register what would be it's the correct value?

Here's the changes I've made so far

In arch/arm64/boot/dts/freescale/imx8mn-evk.dts

+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ >;
+ };
+

-------

+&uart4 { /* RS232 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+

Inarch/arm64/boot/dts/freescale/imx8mn.dtsi

+ uart4: serial@30a60000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30a60000 0x10000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
+ <&clk IMX8MN_CLK_UART4_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };

Best regards, Thiago.

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davidvescovi
Contributor IV

actually it does not help. UART4 is not allocated to any A53 domain. It is used for M4 debug. To use it with a53 there is a low level register at 303d0518 that needs to be reprogrammed. I can not for the life of me find out where this register is initially set.

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diegoadrian
NXP Employee
NXP Employee

Hello,

The module in charge that is in charge of giving the resource domain for the peripherals between cores, is the RDC. If you go to the table 3-3 of the i.MX8MM reference manual, you will see that the UART4 is mapped on the RDC. In this case, the UART4 can be shared between the i.MX8MM cores.

Best regards,

Diego.

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davidvescovi
Contributor IV

I understand this and the 303d0518 is the RDC register that corrects the problem. changing it from 0xfc to 0xff maps it back to a53 cores to use. I just can't find where in the code it is initially set to 0xfc.

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diegoadrian
NXP Employee
NXP Employee

Hello,

You could try modifying the imx8mm_bl31_setup.c file.

Is located in the following path:

$ <your build directory>/tmp/work/imx8mmevk-poky-linux/imx-atf/2.0+gitAUTOINC+1cb68fa0a0-r0/git/plat/imx/imx8mm/imx8mm_bl31_setup.c.

You need to modify the line from.:

mmio_write_32(IMX_RDC_BASE + 0x518, 0xfc);

to:

mmio_write_32(IMX_RDC_BASE + 0x518, 0xff);

This will give read and write access to the domain 0.

Hope this could help you.

Best regards,

Diego.

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Graeme1
Contributor I

Hi, a number of questions here:

How do I get this change into my board ?

Is this file part of the u-boot (and if so, how do I get this into the u-boot configuration)

I 'think' I see this file in the imx-boot-tools in the Yocto deploy directory but I have no idea how to get this file recreated.

(and hence the version of u-boot and the flash-evk that is needed to download using the uuu tool)

 

Also, the file reference is considerably different to what is listed on this page.

The only reference to UART 4 in the bl31 file now looks like this:

static const struct imx_rdc_cfg rdc[] = {
/* Master domain assignment */
RDC_MDAn(RDC_MDA_M4, DID1),

/* peripherals domain permission */
// GrJo - 2021_01_12 - this is totally different to anything I can find on NXP forums or anywhere else on the web
// Taking a guess at what this needs to be (trying to enable UART4 gives a kernel oops)
// RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
RDC_PDAPn(RDC_PDAP_UART4, D0R | D0W),
RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),

/* memory region */

/* Sentinel */
{0},
};

Is the change I made correct - if so Im guessing its that this file has not been update into the uboot build.

 

Also, on the assumption that I cant get the uart4 to work - can I still take control of these pins and manually bitbash them to do software serial.

Or will the uart4 H/W keep control of them - such that I cant do anything in my application ?

 

 

Any help on this greatly appreciated.

Graeme

 

 

 

 

 

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BiyongSUN
NXP Employee
NXP Employee

It is atf code. 

Please check the following link

Re: imx8m mini uart4 - NXP Community

 

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diegoadrian
NXP Employee
NXP Employee

Hello,

If you are trying to route the UART trought the ECSPI2 pin please modify the MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX from  0x00000116 to 0x00001916. Otherwise, I suggest you to rout the UART4 pin to their respective pin and should be configured as following:

MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x00000116
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x00000116

Hope this information could help you.

Best regards,

Diego.

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