IMX8 M4-A53 Shared Memory

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IMX8 M4-A53 Shared Memory

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BradCarey
Contributor I

Does anyone know how much shared memory can be configured between the IMX8M M4 and A53 cores?

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi BRAD

one can look for available ddr memory in sect.2.1.3 Cortex-M4 Memory Map

i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual

Sharing is performed using RDC module described in sect.3.2 Resource Domain Controller (RDC).

Best regards
igor
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edward_fu
Contributor III

Hi igor,

As you said, we can see there are 2GB(0x40000000 - 0xBFFFFFFF) ddr memory in imx8mq Cortex-M4 region. It means there are 2GB memory can be shared between the IMX8M M4 and A53 cores? If so, I encounted problem when run rpmsg_lite_str_echo_rtos as below:

when imx8mq rpmsg shared memory configured as 0xb8400000, the rpmsg demo does not work.

rpmsg_dma_reserved:rpmsg_dma@0xb8400000 {
compatible = "shared-dma-pool";
no-map;
reg = <0 0xb8400000 0 0x100000>;
};

when I configure imx8mq rpmsg shared memory as 0x44040000, the rpmsg demo works.

rpmsg_dma_reserved:rpmsg_dma@0x44040000 {
compatible = "shared-dma-pool";
no-map;
reg = <0 0x44040000 0 0x100000>;
};

&rpmsg{
/*
* 64K for one rpmsg instance:
* --0xb8000000~0xb800ffff: pingpong
*/
vdev-nums = <1>;
reg = <0x0 0xb8000000 0x0 0x10000>;
memory-region = <&rpmsg_dma_reserved>;
status = "okay";
};

If I understand correctly, 0xb8400000 and 0x44040000 are all in 0x40000000 - 0xBFFFFFFF range, so what's the problem? Is it because coniguring RDC error? But how to configure RDC in linux side and where is the source code?

Thanks

Br,

Edward

 

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