IMX8 Initialization system counter

[AFR89]

Hello,

I try to understand how the CNTPCT_EL0 is reset to 0 at power up.
The datasheet of the A35 core say it modified by using CNTVALUEB.
CNTVALUEB seem to be connected to system counter but i don't find any information in the datasheet about the reset. 
Can you give me in which document the reset of this counter is explain?

Best regards

[brian14]

Hi @AFR89,

Thank you for contacting NXP Support. 

I will check this information with our internal team. 

Have a great day! 

[brian14]

Hi @AFR89,

Based on the reply from our expert team, the CNTPCT_EL0 is provided to the ARM cores via the SCU SYSCNTR (system counter). This SYSCNTR is reset to POR (Power-on-Reset). So, during the power-up and if the PMIC resets the system.  Note, the SYSCNTR of the SCU is distributed both to Cortex-A (via CNTPCT_EL0), and to Cortex-M (via its TSTMR counter). It is the same timer that will be read by the SCU, Cortex-A and Cortex-M. Useful for synchronizing them.

[AFR89]

Hello,

Do you have any documentation that explain this behavior? We will need it

Best regards

Alexandre

[brian14]

Hi @AFR89,

This documentation is shared under NDA.

Please submit a support ticket, to review your case. 

Have a great day!