IMX7 RGMii KSZ8795 interface issues and U-Boot testing.

[davidsabalesky]

I am working with Compulab's IMX7 SOM and KSZ8795CLX Ethernet switch, 4 PHY and 1 GMAC.

I now have the correct TXn - TXn, RXn-RXn signal pairings - original RXn-TXn pair was incorrect.

I believe I also need a 125MHz signal as a ref clock pin on the SOM, ENET_REF_CLK.

Can I use the RXCLK from the PHY as the source for this signal?

I am checking with Compulab on what SOM pin they use in their initial setup for this reference clock for testing.

I understand clock delays may need to be added either by PCB trace or internal registers to accommodate Gig speed.

Does the IMX7 have internal registers that can set these delays?

We are using only Mii (MDC/MDIO) interface to the KSZ8795 and  there is no access to clock skew registers in the PHY.

Trace delay is simple and adds approx 9.8in length at 1.8ns. This is a relatively long trace where my routing is limited.

I can use a clock buffer as well to add delay and not worry about increase in trace length.

If anyone has a schematic using IMX7 and KSX8795, please forward link.

I am testing right now the RGMii interface using U-Boot MII.

I can see the PHY registers using Mii, however the RGMii port cannot ping from U-Boot, even at 10/100MBs speeds.

What additional setups if any needed to be made to fully test from U-Boot?

From what I have read you can ping and test functionality of RGMii from U-Boot.

Any suggestions?

Your help is greatly appreciated.

Sincerely,
David

[davidsabalesky]

Hi Yuri,

Please direct me to the documentation where I can set up the reference clock in U-boot.

Can I test the RGMii interface in U-boot? How is this done?

I am working at the lower levels to test my connectivity of the  RGMii interface.

Any and all reference materials are much appreciated.

Thanks,
David

[Yuri]

Hello,

   The problem here is, that we do not use Ethernet switch in our board, therefore 

there is no corresponding code for the reference  clock configuring. 

It should be implemented by customers themselves, using NXP (general) documentation.  

Regards,

Yuri.

[Yuri]

Hello,

  Generally there is no need for (ENET) external reference clock for i.MX7 RGMII.

Also, please look at section 5 (Ethernet connections) of the Hardware Development Guide.

<http://www.nxp.com/assets/documents/data/en/user-guides/IMX7DSHDG.pdf >

 As for Phy-less (MAC-to-MAC) RGMII connections, please refer to slides 18 - 25 of the

following presentation, where the following “external 125 MHz clock source is needed”

is stated.

< https://www.nxp.com/docs/en/supporting-information/WBNR_FTF10_NET_F0568.pdf >

 Table 5-11 (Clock Root Table) of the i.MX 7Dual Reference Manual, Rev. 1, 01/2018,

shows ENET1_REF_CLK_ROOT and ENET2_REF_CLK_ROOT sources. In particular EXT_CLK4

option is available. Table 5-10 (CCM External Signals) shows possible pins for CCM_EXT_CLK4.

In particular, ENET1_COL in ALT6 mode may be used as input reference clock.

  So, it is needed to configure the ref clock under U-boot / Linux. Please refer to chapter about porting

Ethernet of “i.MX_BSP_Porting_Guide.pdf” in Your NXP Linux BSP documentation for more details.

Have a great day,
Yuri

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