IMX6ULL DDR3 DEBUG

[dibing]

Hi,

We designed a monitoring system using IMX6ULL processor and 1GB DDR3 RAM. There is two DDR3 chips with 512MB.

But, the first DDR chip with chip select 0 (CS0) is neither good nor working properly.

If we are removing the Bad DDR chip1, then can we use the second DDR chip with CS0 by shorting DRAM_CS0 and DRAM_CS1 ?

[igorpadykov]

Hi Dibin

shorting DRAM_CS0 and DRAM_CS1 is not allowed, in general one can try to debug

it with jtag (write/read to ddr memory locations and checking waveforms with oscilloscope)

using scripts from ddr test package

i.MX6/7 DDR Stress Test Tool V3.00 

Other options may be running ddr test in lower frequencies and checking power supplies

ripples, should be < 5% as described in Hardware Development Guide for the i.MX6ULL
https://www.nxp.com/docs/en/user-guide/IMX6ULLHDG.pdf

Best regards
igor
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[dibing]

Thanks