Thanks a lot for the suggestion.
Indeed, doing DDR initialization from gdb server was the way to go. We have now access to DDR but the next problem we see when downloading the binary through JTAG is that debugger writes the binary in chunks and reads them back to verify that write operation was successful. In there is a mismatch between written and read data. The following is a log snippet of such operation:
03-00000000-00-00001948-002A: Downloading 996 bytes @ address 0x17800000
02-00000000-00-00001949-0042: TD9BF8640 001:948.990 JLINK_WriteMem(0x17800000, 0x3E4 Bytes, ...)
02-00000000-00-00001949-0052: TD9BF8640 001:949.000 Data: B8 00 00 EA 14 F0 9F E5 14 F0 9F E5 14 F0 9F E5 ...
02-00000000-00-00001949-003C: TD9BF8640 001:949.504 CPU_WriteMem(996 bytes @ 0x17800000)
02-00000000-00-00001970-002E: TD9BF8640 001:970.074 - 21.091ms returns 0x3E4
02-00000000-00-00001970-0041: TD9BF8640 001:970.124 JLINK_ReadMem(0x17800000, 0x3E4 Bytes, ...)
02-00000000-00-00001970-003B: TD9BF8640 001:970.155 CPU_ReadMem(996 bytes @ 0x17800000)
02-00000000-00-00001988-0052: TD9BF8640 001:988.726 Data: B8 00 9F 00 14 F0 80 E5 14 F0 9F E5 14 F0 80 E5 ...
02-00000000-00-00001988-002A: TD9BF8640 001:988.764 - 18.644ms returns 0
03-00000000-00-00001988-0011: - Verify failed
One can see that written bytes are not all the same as read bytes.
Using of UUU tool to flash the same binary to DDR memory through the USB port passes without problems and i can see in serial port that the binary is starting.
I tried to tune some DDR initialization register values with help of NXP's DDR Stress Tester calibration tool but with the same result. Similarly, when I run DDR calibration tool via USB it works, however, when trying to run the calibration over JTAG, the test starts but after several message like "HC_DEL=0x00000000⇥ result[00]=0x11111111" it stops with the following output:
ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.
Error: failed during ddr calibration
Is it possible that JTAG somehow influences DDR operation? Or maybe there are some hardware constrains for JTAG to successfully operation with i.MX6?
One other question is about Register Programming Aid v2.4 for IMX6DQ. We have 4 DDR3 chips all connected to CS0 and each of which is 8Gb (i.e. 16 bit row, 11 bit column and 8 banks). This should indeed give 1GB per chip since 0x10000 * 0x800 * 8 = 1GB. So the DRAM configuration in XLS looks as follows:
However, when we load from this XLS generated INC file to DDR Test tool, it prints the following summary:
It is unclear from where this 8192MB appeared as one would expect to see 4096MB?
Update:
As i mentioned in the previous post i used the following configuration in XLS file of Register Programming Aid 2.4.
However, i could not use the generated INC file to calibrate the DDR further because the DDR Test tool hangs and from USB sound I assume that this is due to restart of attached USB controller (maybe due to restart of device). This is the log message at which DDR Test tool 3.0.0 stops:
============================================
DDR Stress Test (3.0.0)
Build: Dec 14 2018, 14:12:06
NXP Semiconductors.
============================================
============================================
Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.5
============================================
============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00005870
SRC_SBMR2(0x020d801c) = 0x02000011
============================================
ARM Clock set to 1GHz
============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 16, col size: 11
Chip select CSD0 is used
Density per chip select: 8192MB
============================================
Current Temperature: 47
============================================
DDR Freq: 528 MHz
ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
MPWLHWERR register read out for factory diagnostics:
MPWLHWERR PHY0 = 0x3c3c1e1e
MPWLHWERR PHY1 = 0x3c3c3c78
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00330021
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x003C0046
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x003A0036
Write DQS delay result:
Write DQS0 delay: 31/256 CK
Write DQS1 delay: 31/256 CK
Write DQS2 delay: 33/256 CK
Write DQS3 delay: 51/256 CK
Write DQS4 delay: 70/256 CK
Write DQS5 delay: 60/256 CK
Write DQS6 delay: 54/256 CK
As one can see the tool calculates the density per chip select as 8192 MB, but it should be 4096 MB.
We have 4 DDR chips using a single CS0 and each of which is 1 Gb (with 16 bit row, 11 bit column and 8 banks).
So the wrong density per chip which the DDT Test tool calculates may be the reason of its hanging.
Using the JTAG version of DDR Stress Test gives the following output:
Starting DQS gating calibration
. HC_DEL=0x00000000⇥ result[00]=0x11111111
. HC_DEL=0x00000001⇥ result[01]=0x11111111
. HC_DEL=0x00000002⇥ result[02]=0x11111111
. HC_DEL=0x00000003⇥ result[03]=0x11111111
. HC_DEL=0x00000004⇥ result[04]=0x11111111
. HC_DEL=0x00000005⇥ result[05]=0x11111111
. HC_DEL=0x00000006⇥ result[06]=0x11111111
. HC_DEL=0x00000007⇥ result[07]=0x11111111
. HC_DEL=0x00000008⇥ result[08]=0x11111111
. HC_DEL=0x00000009⇥ result[09]=0x11111111
. HC_DEL=0x0000000A⇥ result[0A]=0x11111111
. HC_DEL=0x0000000B⇥ result[0B]=0x11111111
. HC_DEL=0x0000000C⇥ result[0C]=0x11111111
. HC_DEL=0x0000000D⇥ result[0D]=0x11111111
ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.
Error: failed during ddr calibration
But i am inclined to think that the generated INC file is correct because when using its data for JTAG debugging, i can finally see that some chunks that are downloaded into DDR the result of the verification is OK.
So, it seems that it is simply because of uncalibrated INC file data that i use to download the u-boot binary gives for some downloaded chunks "Verify failed". Unfortunately, i cannot calibrate the DDR memory with generated INC neither with DDR Stress Test tool (for the reason already mentioned) nor with JTAG variant of DDR Test tool. Both ways fails.
Is it possible to somehow convince the DDR Stress Test GUI program to correctly calculate the DDR density?
