IMX6DQ6SDLHDG pdf

[jburk]

Regarding section 3.5.6 Four chips T topology routing examples: the pdf shows three layers of DDR3 routing, but there is clearly a fourth layer used that isn't shown. Would it be possible to get a screenshot of the missing layer?

[art]

Generally, for all routing examples, refer to the i.MX6Q SABRE SD board PCB

design files, available as the i.MX6_SABRE_SDP_DESIGNFILES package on the NXP

web site (check the "Schematics" section):

http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-process...

Have a great day,
Artur

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