Here is the full output of DDR tool.
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DDR Stress Test (2.6.0)
Build: Jan 24 2018, 14:20:57
NXP Semiconductors.
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Chip ID
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.3
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Boot Configuration
SRC_SBMR1(0x020d8004) = 0x18002840
SRC_SBMR2(0x020d801c) = 0x02000001
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ARM Clock set to 1GHz
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DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 14, col size: 10
Chip select CSD0 is used
Density per chip select: 1024MB
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Current Temperature: 48
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DDR Freq: 396 MHz
ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0064006C
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x004E005A
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x003D0046
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x0028003F
Write DQS delay result:
Write DQS0 delay: 108/256 CK
Write DQS1 delay: 100/256 CK
Write DQS2 delay: 90/256 CK
Write DQS3 delay: 78/256 CK
Write DQS4 delay: 70/256 CK
Write DQS5 delay: 61/256 CK
Write DQS6 delay: 63/256 CK
Write DQS7 delay: 40/256 CK
Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x11111111
. HC_DEL=0x00000001 result[01]=0x00111111
. HC_DEL=0x00000002 result[02]=0x00000000
. HC_DEL=0x00000003 result[03]=0x00000000
. HC_DEL=0x00000004 result[04]=0x11111100
. HC_DEL=0x00000005 result[05]=0x11111111
. HC_DEL=0x00000006 result[06]=0x11111111
. HC_DEL=0x00000007 result[07]=0x11111111
. HC_DEL=0x00000008 result[08]=0x11111111
. HC_DEL=0x00000009 result[09]=0x11111111
. HC_DEL=0x0000000A result[0A]=0x11111111
. HC_DEL=0x0000000B result[0B]=0x11111111
. HC_DEL=0x0000000C result[0C]=0x11111111
. HC_DEL=0x0000000D result[0D]=0x11111111
DQS HC delay value low1 = 0x02020202, high1=0x03030404
DQS HC delay value low2 = 0x01010202, high2=0x03030303
loop ABS offset to get HW_DG_LOW
. ABS_OFFSET=0x00000000 result[00]=0x11111111
. ABS_OFFSET=0x00000004 result[01]=0x11111111
. ABS_OFFSET=0x00000008 result[02]=0x11111111
. ABS_OFFSET=0x0000000C result[03]=0x11111111
. ABS_OFFSET=0x00000010 result[04]=0x11111111
. ABS_OFFSET=0x00000014 result[05]=0x11111111
. ABS_OFFSET=0x00000018 result[06]=0x11111111
. ABS_OFFSET=0x0000001C result[07]=0x11111111
. ABS_OFFSET=0x00000020 result[08]=0x11010011
. ABS_OFFSET=0x00000024 result[09]=0x11010011
. ABS_OFFSET=0x00000028 result[0A]=0x11000011
. ABS_OFFSET=0x0000002C result[0B]=0x11010011
. ABS_OFFSET=0x00000030 result[0C]=0x11000011
. ABS_OFFSET=0x00000034 result[0D]=0x11000011
. ABS_OFFSET=0x00000038 result[0E]=0x11000011
. ABS_OFFSET=0x0000003C result[0F]=0x11000011
. ABS_OFFSET=0x00000040 result[10]=0x11000011
. ABS_OFFSET=0x00000044 result[11]=0x11000011
. ABS_OFFSET=0x00000048 result[12]=0x11000010
. ABS_OFFSET=0x0000004C result[13]=0x11000000
. ABS_OFFSET=0x00000050 result[14]=0x11000000
. ABS_OFFSET=0x00000054 result[15]=0x11000000
. ABS_OFFSET=0x00000058 result[16]=0x11000000
. ABS_OFFSET=0x0000005C result[17]=0x11000000
. ABS_OFFSET=0x00000060 result[18]=0x11000000
. ABS_OFFSET=0x00000064 result[19]=0x11000000
. ABS_OFFSET=0x00000068 result[1A]=0x11000000
. ABS_OFFSET=0x0000006C result[1B]=0x11000000
. ABS_OFFSET=0x00000070 result[1C]=0x11000000
. ABS_OFFSET=0x00000074 result[1D]=0x11000000
. ABS_OFFSET=0x00000078 result[1E]=0x11000000
. ABS_OFFSET=0x0000007C result[1F]=0x11000000
loop ABS offset to get HW_DG_HIGH
. ABS_OFFSET=0x00000000 result[00]=0x00000000
. ABS_OFFSET=0x00000004 result[01]=0x00000000
. ABS_OFFSET=0x00000008 result[02]=0x00000000
. ABS_OFFSET=0x0000000C result[03]=0x00000000
. ABS_OFFSET=0x00000010 result[04]=0x00000001
. ABS_OFFSET=0x00000014 result[05]=0x00000001
. ABS_OFFSET=0x00000018 result[06]=0x00000001
. ABS_OFFSET=0x0000001C result[07]=0x00000011
. ABS_OFFSET=0x00000020 result[08]=0x00000011
. ABS_OFFSET=0x00000024 result[09]=0x00000011
. ABS_OFFSET=0x00000028 result[0A]=0x00000011
. ABS_OFFSET=0x0000002C result[0B]=0x00000011
. ABS_OFFSET=0x00000030 result[0C]=0x00000011
. ABS_OFFSET=0x00000034 result[0D]=0x00000011
. ABS_OFFSET=0x00000038 result[0E]=0x00000011
. ABS_OFFSET=0x0000003C result[0F]=0x10000011
. ABS_OFFSET=0x00000040 result[10]=0x10000011
. ABS_OFFSET=0x00000044 result[11]=0x10000011
. ABS_OFFSET=0x00000048 result[12]=0x11000011
. ABS_OFFSET=0x0000004C result[13]=0x11000011
. ABS_OFFSET=0x00000050 result[14]=0x11000011
. ABS_OFFSET=0x00000054 result[15]=0x11000011
. ABS_OFFSET=0x00000058 result[16]=0x11000011
. ABS_OFFSET=0x0000005C result[17]=0x11001111
. ABS_OFFSET=0x00000060 result[18]=0x11001111
. ABS_OFFSET=0x00000064 result[19]=0x11101111
. ABS_OFFSET=0x00000068 result[1A]=0x11101111
. ABS_OFFSET=0x0000006C result[1B]=0x11111111
. ABS_OFFSET=0x00000070 result[1C]=0x11111111
. ABS_OFFSET=0x00000074 result[1D]=0x11111111
. ABS_OFFSET=0x00000078 result[1E]=0x11111111
. ABS_OFFSET=0x0000007C result[1F]=0x11111111
BYTE 0:
Start: HC=0x01 ABS=0x48
End: HC=0x04 ABS=0x0C
Mean: HC=0x02 ABS=0x69
End-0.5*tCK: HC=0x03 ABS=0x0C
Final: HC=0x03 ABS=0x0C
BYTE 1:
Start: HC=0x01 ABS=0x4C
End: HC=0x04 ABS=0x18
Mean: HC=0x02 ABS=0x71
End-0.5*tCK: HC=0x03 ABS=0x18
Final: HC=0x03 ABS=0x18
BYTE 2:
Start: HC=0x01 ABS=0x20
End: HC=0x03 ABS=0x58
Mean: HC=0x02 ABS=0x3C
End-0.5*tCK: HC=0x02 ABS=0x58
Final: HC=0x02 ABS=0x58
BYTE 3:
Start: HC=0x01 ABS=0x20
End: HC=0x03 ABS=0x58
Mean: HC=0x02 ABS=0x3C
End-0.5*tCK: HC=0x02 ABS=0x58
Final: HC=0x02 ABS=0x58
BYTE 4:
Start: HC=0x01 ABS=0x30
End: HC=0x03 ABS=0x68
Mean: HC=0x02 ABS=0x4C
End-0.5*tCK: HC=0x02 ABS=0x68
Final: HC=0x02 ABS=0x68
BYTE 5:
Start: HC=0x01 ABS=0x20
End: HC=0x03 ABS=0x60
Mean: HC=0x02 ABS=0x40
End-0.5*tCK: HC=0x02 ABS=0x60
Final: HC=0x02 ABS=0x60
BYTE 6:
Start: HC=0x01 ABS=0x00
End: HC=0x03 ABS=0x44
Mean: HC=0x02 ABS=0x22
End-0.5*tCK: HC=0x02 ABS=0x44
Final: HC=0x02 ABS=0x44
BYTE 7:
Start: HC=0x01 ABS=0x00
End: HC=0x03 ABS=0x38
Mean: HC=0x02 ABS=0x1C
End-0.5*tCK: HC=0x02 ABS=0x38
Final: HC=0x02 ABS=0x38
DQS calibration MMDC0 MPDGCTRL0 = 0x0318030C, MPDGCTRL1 = 0x02580258
DQS calibration MMDC1 MPDGCTRL0 = 0x02600268, MPDGCTRL1 = 0x02380244
Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 00000001:byte 0 fail.
result 00000011:byte 0, 1 fail.
Starting Read calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x11111111
ABS_OFFSET=0x08080808 result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x11111111
ABS_OFFSET=0x10101010 result[04]=0x11111111
ABS_OFFSET=0x14141414 result[05]=0x11111111
ABS_OFFSET=0x18181818 result[06]=0x11111111
ABS_OFFSET=0x1C1C1C1C result[07]=0x11111111
ABS_OFFSET=0x20202020 result[08]=0x11111111
ABS_OFFSET=0x24242424 result[09]=0x11111111
ABS_OFFSET=0x28282828 result[0A]=0x11111010
ABS_OFFSET=0x2C2C2C2C result[0B]=0x11100000
ABS_OFFSET=0x30303030 result[0C]=0x01000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000000
ABS_OFFSET=0x58585858 result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
ABS_OFFSET=0x60606060 result[18]=0x00000000
ABS_OFFSET=0x64646464 result[19]=0x00000000
ABS_OFFSET=0x68686868 result[1A]=0x00000000
ABS_OFFSET=0x6C6C6C6C result[1B]=0x00001100
ABS_OFFSET=0x70707070 result[1C]=0x00011111
ABS_OFFSET=0x74747474 result[1D]=0x10011111
ABS_OFFSET=0x78787878 result[1E]=0x10111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
Byte 0: (0x28 - 0x6c), middle value:0x4a
Byte 1: (0x2c - 0x6c), middle value:0x4c
Byte 2: (0x28 - 0x68), middle value:0x48
Byte 3: (0x2c - 0x68), middle value:0x4a
Byte 4: (0x2c - 0x6c), middle value:0x4c
Byte 5: (0x30 - 0x74), middle value:0x52
Byte 6: (0x34 - 0x78), middle value:0x56
Byte 7: (0x30 - 0x70), middle value:0x50
MMDC0 MPRDDLCTL = 0x4A484C4A, MMDC1 MPRDDLCTL = 0x5056524C
Starting Write calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111110
ABS_OFFSET=0x04040404 result[01]=0x10101000
ABS_OFFSET=0x08080808 result[02]=0x10100000
ABS_OFFSET=0x0C0C0C0C result[03]=0x10000000
ABS_OFFSET=0x10101010 result[04]=0x10000000
ABS_OFFSET=0x14141414 result[05]=0x00000000
ABS_OFFSET=0x18181818 result[06]=0x00000000
ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00010010
ABS_OFFSET=0x50505050 result[14]=0x00010010
ABS_OFFSET=0x54545454 result[15]=0x00010110
ABS_OFFSET=0x58585858 result[16]=0x00010110
ABS_OFFSET=0x5C5C5C5C result[17]=0x11111111
ABS_OFFSET=0x60606060 result[18]=0x11111111
ABS_OFFSET=0x64646464 result[19]=0x11111111
ABS_OFFSET=0x68686868 result[1A]=0x11111111
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111
ABS_OFFSET=0x70707070 result[1C]=0x11111111
ABS_OFFSET=0x74747474 result[1D]=0x11111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
Byte 0: (0x00 - 0x58), middle value:0x2c
Byte 1: (0x04 - 0x48), middle value:0x26
Byte 2: (0x04 - 0x50), middle value:0x2a
Byte 3: (0x08 - 0x58), middle value:0x30
Byte 5: (0x0c - 0x58), middle value:0x32
Byte 6: (0x04 - 0x58), middle value:0x2e
Byte 7: (0x14 - 0x58), middle value:0x36
MMDC0 MPWRDLCTL = 0x302A262C,MMDC1 MPWRDLCTL = 0x362E3226
MMDC registers updated from calibration
Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0064006C
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x004E005A
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x003D0046
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x0028003F
Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x0318030C
MPDGCTRL1 PHY0 (0x021b0840) = 0x02580258
MPDGCTRL0 PHY1 (0x021b483c) = 0x02600268
MPDGCTRL1 PHY1 (0x021b4840) = 0x02380244
Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x4A484C4A
MPRDDLCTL PHY1 (0x021b4848) = 0x5056524C
Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x302A262C
MPWRDLCTL PHY1 (0x021b4850) = 0x362E3226
Success: DDR calibration completed!!!