IMX6D4AVT10AC

[tomcoggio]

I have a puzzling question. I have an in house design using Micron MT42L256M64D4LM-25 WT

1.I am running the Stress tool to test the LPDDR2 memory.

     DDR Stress Test (1.0.3) for MX6DQ

    Build: Jun 25 2014, 12:09:21

    Freescale Semiconductor, Inc.

2. I get consistent  PASSes for ARM core speed 800MHz and DDR freq of 400MHz

    I also get consistent PASSes for ARM core speed 1GHz and DDR freq of 380MHz

but

   I get a consistent FAIL  for ARM core speed 1GHz and DDR freq of 400MHz

here's part of what I get

Test channel 0

ABS_OFFSET=0x00000000   result[00]=0x1111

ABS_OFFSET=0x04040404   result[01]=0x1111

ABS_OFFSET=0x08080808   result[02]=0x1111

ABS_OFFSET=0x0C0C0C0C   result[03]=0x1111

ABS_OFFSET=0x10101010   result[04]=0x1111

ABS_OFFSET=0x14141414   result[05]=0x1111

ABS_OFFSET=0x18181818   result[06]=0x1111

ABS_OFFSET=0x1C1C1C1C   result[07]=0x1111

ABS_OFFSET=0x20202020   result[08]=0x0011

ABS_OFFSET=0x24242424   result[09]=0x0011

ABS_OFFSET=0x28282828   result[0A]=0x0011

ABS_OFFSET=0x2C2C2C2C   result[0B]=0x0011

ABS_OFFSET=0x30303030   result[0C]=0x0011

ABS_OFFSET=0x34343434   result[0D]=0x0011

ABS_OFFSET=0x38383838   result[0E]=0x0011

ABS_OFFSET=0x3C3C3C3C   result[0F]=0x0011

ABS_OFFSET=0x40404040   result[10]=0x0011

ABS_OFFSET=0x44444444   result[11]=0x0011

ABS_OFFSET=0x48484848   result[12]=0x0011

ABS_OFFSET=0x4C4C4C4C   result[13]=0x0011

ABS_OFFSET=0x50505050   result[14]=0x0011

ABS_OFFSET=0x54545454   result[15]=0x1111

allways the lower 2 bytes.

I can't understand why it is different at 1 GHz as I understand the PLL for the memory is still originating from the 24MHz external xtal.

and the ARM PLL is separate from the System PLL.

Any ideas?

[igorpadykov]

Hi tom

please look at sect.3.3.1 Identifying Issue on Calibrations

MX6 DRAM Port Application Guide where this issue is described

Freescale i.MX6 DRAM Port Application Guide-DDR3

Best regards

igor

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[tomcoggio]

Hi Igor,

I've read the link, although we are using LPDDR2 not DDR3, I have tryed all those thing sugested.

The SDRAM goes perfectly on all the test Rd, Write, Loop tests, Single, double channel, interleaved all OK for all the tests as I posted

2. I get consistent  PASSes for ARM core speed 800MHz and DDR freq of 400MHz

    I also get consistent PASSes for ARM core speed 1GHz and DDR freq of 380MHz

but

   I get a consistent FAIL  for ARM core speed 1GHz and DDR freq of 400MHz (396MHz)

If you look at the CCM clock tree for the processor, PLL1 is independent and produces the ARM_CLK_ROOT

PLL2 /PFDO-2  feeds the Memory Clock which goes to produce MMDC_CHx_CLK_ROOT.

Both of these PLL's originate from the same source (the external 24MHz xtal) I'm starting to suspect an unstable X-tal (too much jitter)

Thanks

Tom

[igorpadykov · Accepted solution]

Hi Tom

one can look at below link giving suggestions for configuration with lpddr2

MX6Q+LPDDR2(32bit) boot issue

Best regards

igor

[tomcoggio]

Thanks for your help Igor. I will look at this issue more closely in a few weeks time.