IMX6D LVDS not working

[lyashmik]

I am trying to setup LVDS display on IMX6D which is working only through LVDS1 channel. The display is LG lb070wv8-sl02 (datasheet attached). I have changed imx6qdl-sabresd.dtsi like this:

mxcfb1: fb@0 {
		compatible = "fsl,mxc_sdc_fb";
		disp_dev = "ldb";
		interface_pix_fmt = "RGB24";
		default_bpp = <24>;
		int_clk = <0>;
		late_init = <0>;
		status = "okay";
	};
&ldb {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;
    compatible = "fsl,imx6q-ldb";
	gpr = <&gpr>;
	primary;

	lvds-channel@0 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;
		status = "disabled";

		display-timings {
			native-mode = <&timing0>;
			timing0: hsd100pxn1 {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <220>;
				hfront-porch = <40>;
				vback-porch = <21>;
				vfront-porch = <7>;
				hsync-len = <60>;
				vsync-len = <10>;
			};
		};
	};

	lvds-channel@1 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <24>;
		primary;
		status = "okay";

		display-timings {
			native-mode = <&timing1>;
			timing1: LB070WV8_SL02_800X480 {
				clock-frequency = <34000000>;
				hactive = <800>;
				vactive = <480>;
				hback-porch = <160>;
				hfront-porch = <80>;
				vback-porch = <25>;
				vfront-porch = <15>;
				hsync-len = <256>;
				vsync-len = <45>;
 			};
		};
	};
};

And I've also changed bootargs in uboot like this:

Kernel command line: console=ttymxc0,115200 root=/dev/mmcblk2p2 rootwait rw video=mxcfb0:dev=ldb,if=RGB24 ldb=sin1 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off

Looking into fbset it seems that it shows the right values, if I understand correctly:

# fbset

mode "800x480-46"
        #  34.001 MHz, H: 26.235 kHz, V: 46.434 Hz
        geometry 800 480 800 480 24
        timings 29411 160 80 25 15 256 45
        accel false
        rgba 8/16,8/8,8/0,0/0
endmode

Here is the dmesg logs concerning fb:

[    0.000000] Kernel command line: console=ttymxc0,115200 root=/dev/mmcblk2p2 rootwait rw video=mxcfb0:dev=ldb,if=RGB24 ldb=sin1 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off
[    1.118132] mxc_sdc_fb fb@0: registered mxc display driver ldb
[    1.118496] mxc_sdc_fb fb@1: Can't get fb option for mxcfb1!
[    1.118840] mxc_sdc_fb fb@2: Can't get fb option for mxcfb2!
[    1.119178] mxc_sdc_fb fb@3: Can't get fb option for mxcfb3!
[    3.856214] mxc_sdc_fb fb@0: registered mxc display driver ldb
[    4.497348] mxc_sdc_fb fb@0: timeout when waiting for flip irq

 The only thing concerning me here is "timeout when waiting for flip irq" message, but I don't know if this could cause the display to not initialize correctly and what stands behind this.

Could you please help me at least with the steps to identify the issue causing the display to not work, because I don't know where else to look. Thanks.

I am using uboot-imx lf_v2023.04 and linux-imx lf-6.1.1-1.0.1

[Bio_TICFSL]

Hello,

You better change the kernel since this version is not supported. now the I think the error is hapens on lvds clock rate

clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);

in ipu_disp.c

Above will use g_pixel_clk set_rate function to set clock rate which approach panel pixel rate we defined in display structure. In set_rate function, it will use g_pixel_clk parent, which is g_ldb_clk as a divider to calculate. After calculate, it will set DI_BS_CLKGEN0 and DI_BS_CLKGEN1 register to let IPU pixel clock sync with LDB clock. But g_ldb_clock has been always set to 65MHz, that means a lot of clock rate cannot be divide, then IPU pixel clock will not sync with LDB clock, so display cannot output anything.

As I know, g_pixel_clk which should use same clock parent as ldb clock. That is what kernel did.

So for short term, just modify g_ldb_clock.rate to same as your ldb clock rate, then ipu_pixel_clk_set_rate can divide clock rate correctly.

regards

[lyashmik]

Hello @Bio_TICFSL ,

Thank you for the reply. I have a couple of questions.
First, what linux kernel version would you recommend to use (branch or tag would be even better).
Second, if I understood you correctly I should try and set ldb_clk (ldb_di1_clk in my case, because only channel 1 is used) to the desired clock after acquiring it, so that then ipu clk would be set to the right value. So I created the following patch:

diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c
index 33ff22ca860f..be0149c6402f 100644
--- a/drivers/mxc/ipu3/ipu_disp.c
+++ b/drivers/mxc/ipu3/ipu_disp.c
@@ -1109,6 +1109,19 @@ int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, uint32_t pixel_clk,
 		dev_err(ipu->dev, "clk_get di1 failed");
 		return PTR_ERR(ldb_di1_clk);
 	}
+	// Attempt to set ldb_di1_clk rate close to pixel_clk
+	ret = clk_set_rate(ldb_di1_clk, pixel_clk);
+	if (ret) {
+		dev_err(ipu->dev, "Failed to set ldb_di1_clk rate: %d\n", ret);
+		return ret;
+	}
+
+	// Set ldb_di1_clk as the parent of pixel_clk to ensure synchronization
+	ret = clk_set_parent(ipu->pixel_clk_sel[disp], ldb_di1_clk);
+	if (ret) {
+		dev_err(ipu->dev, "Failed to set pixel_clk parent to ldb_di1_clk: %d\n", ret);
+		return ret;
+	}
 	if (!strcmp(__clk_get_name(di_parent), __clk_get_name(ldb_di0_clk)) ||
 		!strcmp(__clk_get_name(di_parent), __clk_get_name(ldb_di1_clk))) {
 		/* if di clk parent is tve/ldb, then keep it;*/
-- 
2.34.1

but in response to the changes I get the following error:

imx-ipuv3 2800000.ipu: Failed to set pixel_clk parent to ldb_di1_clk: -22

Please, let me know if I understood you correctly.
Thirdly, a question off topic. I am also trying to enable dev_dbg messages to see them in dmesg by enabling dynamic debug and adding this to the kernel command line:

dyndbg="file ipu_disp.c +p"

but in the kernel boot logs I get the following:

dyndbg: ipu_disp.c="(null)"

Does it mean that it cannot find ipu_disp.c file? Am I configuring this wrong?
Thanks in advance.

Regards