IMX6 with external ethernet reference clock not working

[Kylian]

Background:

I have a custom Imx6ull processor board that has an external ethernet phy and I'm trying to setup networking in the kernel. I've gotten to the point where `ifconfig` shows the interface and the driver is detected. When I plug in an ethernet cable it will also be detected.

Problem:

The network connection is non-functional. Trying to ping anything results in "Network is Unreachable".

(Possible) Cause:

When I measure the ethernet reference clock generated by the external phy (lan8720) I see a clean 50MHz clock. In the device tree i've configured the MX6UL_PAD_ENET1_TX_CLK to ENET1_TX_CLK to make it an input. However when I check the IOMUXC_GPR_GPR1 register with `devmem 0x20E4004 32` it returns that ENET1_CLK_SEL (bit 13) is 0 and ENET1_TX_CLK_DIR (bit 17) is 1. This is exactly the opposite of what I want. I think this is the reason my external clock is not detected but I'm not sure how to change the state of these bits?

Question:
How can I change the state of the ENET1_CLK_SEL and ENET1_TX_CLK_DIR bits? Can I do that through the device tree? If that doesn't fix the problem is there anything else I can try?

My device tree:
```

#include "imx6ull.dtsi"

/ {
chosen {
stdout-path = &uart4;
};

memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x08000000>;
};

watchdog: watchdog {
/* STM6822 */
compatible = "linux,wdt-gpio";
gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
hw_algo = "toggle";
hw_margin_ms = <1500>;
};
};

&cpu0 {
clock-frequency = <528000000>;
};

&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};

&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};

&wdog1 {
fsl,ext-reset-output;
status = "okay";
};

&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
status = "okay";
};

&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,use-minimum-ecc;
status = "okay";
};

&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
local-mac-address = [ 9A 0C AD A0 1D 09 ];
phy-mode = "rmii";
phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
status = "okay";
};

&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
spidev@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <4000000>;
status = "okay";
};
};

&iomuxc {
pinctrl-names = "default";

pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};

pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x79
>;
};

pinctrl_gpmi_nand: nandgrp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x100a9
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
>;
};

pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1
>;
};

pinctrl_fec1: fec1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b1
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b1
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x1b0b1
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b1
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b1
MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x4001b0b1
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b1
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b1
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b1
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b1
MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b1
>;
};

pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x1b0b1
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x1b0b1
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x4001b0b1
MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x1b0b1
>;
}

};

```

[Kylian]

I've managed to change the bits in the GPR1 register by creating a patch for the file 'arch/arm/mach-imx/mach-imx6ul.c' where I hardcode the values. After doing this I still don't have an ethernet connection so I'm out of idea's. All suggestions are welcome

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

That is set through the clock properties assigned in dtsi, please look at these here.

Could you try to read the link status bit through MDIO in u-boot and/or linux after making sure that the MAC is receiving the REF_CLK?

Regards