IMX6 as PCIe endpoint : help requested

[sylvainfabre]

Thanks to the patches available here : i.MX6Q PCIe EP/RC Validation System , i can link 2 boards thru PCIe and write the RC memory.

But now, i need to convert the EP board into a real endpoint, with at least 1 MEM area and 1 IO area. This is done on the EP side with the proper BAR configuration, and the RC recognized it (seen with lspci -v and a custom kernel module). But up to now, i am unable to adress properly the IO BAR from the RC. I guess it is related to the iATU configuration for adresss translation, but my trials are failing up to now.

Shall i configure an inbound translation ? An outbound ? Both ?

Is there someone with a small piece of code showing the whole configuration used to declare/setup an IO space on a IMX6 and to access it from another IMX6 ?

Thanks, SF

[jamesbone]

We are working in your issue we will contact you as soon as we have some more information from our experts team

[sylvainfabre]

Thanks. Any news on that ? I am also interested on working example for sending an interrupt from a IMX6 EP to a IMX6 RC.

[jamesbone]

This is the response from our experts team:

Actually, IMX6 as one endpoint function has been integrated into new release(You can get it in JB4.3 or later).You just need to enable the board config option "CONFIG_IMX_PCIE_EP_MODE_IN_EP_RC_SYS=y". When you connect to anther IMX6 RC board by pcie interface, you can see the following kernel message:

<7>pci 0000:00:00.0: [16c3:abcd] type 1 class 0x000000

<3>pci 0000:00:00.0: ignoring class 00 (doesn't match header type 01)

<7>pci 0000:00:00.0: supports D1

<7>pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold

<7>pci 0000:00:00.0: PME# disabled

<7>pci 0000:01:00.0: [16c3:abcd] type 0 class 0x000000

<7>pci 0000:01:00.0: reg 10: [mem 0x00000000-0x000fffff 64bit pref]

<7>pci 0000:01:00.0: reg 18: [mem 0x00000000-0x000fffff pref]

<7>pci 0000:01:00.0: reg 1c: [io  0x0000-0x00ff]

<7>pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0000ffff pref]

<7>pci 0000:01:00.0: supports D1

<7>pci 0000:01:00.0: PME# supported from D0 D1 D3hot D3cold

<7>pci 0000:01:00.0: PME# disabled

<6>pci 0000:00:00.0: not setting up bridge for bus 0000:01

You can take it as one reference.

[sylvainfabre]

Thanks for your answer, but i just look in to the JB4.3 kernel branch, and the code inside the pcie.c is exactly the one used in the page indicated on my first post.

This code is not a full  EndPoint code : this is a test to allow the EP to write to the RC DDR. IO/Mem BAR access in RW and IT generation are missing.

For example, if we just take the settings you described above, let's try to write in the memory declared in the BAR0 :

- RC side : IO remap of the 0x0110_0000 -> This where the BAR 0 is mapped on the PCIE IO space on RC side

- EP side :

1. Allocate memory with kzalloc (for example) for BAR0
2. Setup the iATU registers (inbound 0) to allow input addresses in 0x0110_0000 to be translated to the allocated memory

- Then memory access on RC side to 0x0110_0000 -> bus error.

I tested various registers settings for the iATU programming, but none of them are woriking.

I you have a working example of this, it would help greatly.

Thanks :smileyhappy: