IMX6 UART2 pin mux definition question

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IMX6 UART2 pin mux definition question

Contributor II

On an IMX6Q design I am using UART2 as the console with signal GPIO 7 as the Trasmit and signal GPIO 8 as the receive. I used the values for the pin muxing found in the file imx6q-pinfunc.h in my device tree file.

I believe I found a problem in the #defines for these signals. First I used the definitions in the imx6q-pinfunc.h to make the device tree file with a 3.10.17 Linux release. I found that the UART2 was not operational and specifically I could not transmit any data from the terminal session attached to UART2. I then went to the documentation for the IMX6DQRM.pdf Document Number: IMX6DQRM Rev 2, 06/2014 to see what could be going on.

After reviewing the documentation of the pin muxing, I have come to the conclusion that the file imx6q-pinfunc.h has a defect. I proved it by making the edits and then booting the resulting Linux kernel to a prompt and observing that UART2 has a working transmit and receive set of signals.

Here is the existing code using branch imx_3.10.17_1.0.1_ga and also Linux version 3,19

#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA  0x244 0x614 0x928 0x4 0x3

#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA  0x244 0x614 0x000 0x4 0x0

#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA  0x240 0x610 0x000 0x4 0x0

#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA  0x240 0x610 0x928 0x4 0x2


// INCORRECT value #define MX6QDL_PAD_GPIO_7__UART2_TX_DATA            0x240 0x610 0x000 0x4 0x0

// REMOVE this the signal is not a receiver #define MX6QDL_PAD_GPIO_7__UART2_RX_DATA            0x240 0x610 0x928 0x4 0x2

#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA            0x240 0x610 0x928 0x4 0x2

// REMOVE this  signal is not a transmitter #define MX6QDL_PAD_GPIO_8__UART2_TX_DATA            0x244 0x614 0x000 0x4 0x0

#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA            0x244 0x614 0x928 0x4 0x3

I would appreciate feedback, perhaps I am missing something but it works for me using UART 2 GPIO 7 as a TX and GPIO 8 as an RX signal.

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2 Replies

NXP TechSupport
NXP TechSupport

The values in “define” table of “imx6q-pinfunc.h” file are pin function ID and
are defined as

<mux_reg conf_reg input_reg mux_mode input_val>

the first item – “mux_reg” - is offset for corresponding IOMUXC_SW_MUX_CTL_PAD_xxx register
“conf_reg” is offset  for IOMUXC_SW_PAD_CTL_PAD_xxx
“input_reg” is offset  for IOMUXC_yyy_SELECT_INPUT (for daisy chain option)
“mux_mode” is data to be written to “mux_reg”
“input_val” is data to be written to “input _reg”

As an example for GPIO08 of i.MX6Q :

Address: 20E_0000h base + 23Ch offset = 20E_023Ch

Address: 20E_0000h base + 60Ch offset = 20E_060Ch

Address: 20E_0000h base + 904h offset = 20E_0904h

So, the GPIO08 pin function ID should be

< 0x244 0x614 0x90C 0x4 0x3 >

    Looks like the pin function ID in “imx6q-pinfunc.h” is incorrect, at least, regarding

Have a great day,

Note: If this post answers your question, please click the Correct Answer button. Thank you!

Contributor II

Patch sent March 10 and reproduced below

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Received: by with HTTP; Tue, 10 Mar 2015 06:45:42 -0700 (PDT)

Date: Tue, 10 Mar 2015 09:45:42 -0400


Message-ID: <>

Subject: [PATCH] ARM: dts: imx: imx6q uart2 pin mux correction

From: Robert Smigielski <>


Cc: Robert Smigielski <>

Content-Type: text/plain; charset=ISO-8859-1

This patch contains a correction to the file imx6q-pinfunc.h for the

definition of the UART2 GPIO pin mux setting.

Issue found when testing UART2 configured as the console in Linux

GPIO_7 is a transmit pin not a transmit and receive pin

GPIO_8 is a receive pin not a transmit and receive pin

Verified the correction with Freescale in posting to the Freescale


commit c383bbb4d17037435305858f488db7ae17dc1c85

Author: robert.smigielski <>

Date: Fri Mar 6 11:53:20 2015 -0500

  UART2 Tx and Rx values corrected based on IMX6Q datasheet

diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h


index c68c21d..4d4cc49 100644

--- a/arch/arm/boot/dts/imx6q-pinfunc.h

+++ b/arch/arm/boot/dts/imx6q-pinfunc.h

@@ -696,8 +696,7 @@

#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0

#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0

#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0

-#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0

-#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2

+#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x928 0x4 0x2

#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0

#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0

#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0

@@ -706,7 +705,6 @@

#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0

#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1

#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3

-#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0

#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0

#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0

#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0

Robert Smigielski

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