IMX6 PCIe Bus issue with pericom switch

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IMX6 PCIe Bus issue with pericom switch

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balashanmugam
Contributor III

Hi FSL community,
    We are working on the project with imx6 qseven module, we are using the pericom PI7C9X2G404SL 4 port switch for bridging. While accessing the end devices connected via this pericom switch, we are facing the following issues.
    1.Some times end devices are detecting and some times not.
    2.Data transfer rate is also too slow, when it is detecting.(pci to usb bridge)
    3.Our kernel version is 3.0.35.

Can you pls assist us to fix this issue. Thanks in advance.

Regards,
Arulpandiyan Vadivel

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igorpadykov
NXP Employee
NXP Employee

Hi Arulpandiyan

slow rate may be caused by weak signal (caused by signal integrity/noise/

layout impedance issues). One can measure signal levels with

AN4784 AN4784: PCIe Certification Guide for i.MX

Also one can decrease PCIe speed, it is defined by  Link Capabilities Register,

described in PCI EXPRESS BASE SPECIFICATION, REV. 3.0,

Table 7-15: Link Capabilities Register, sect.7.8.6. Link Capabilities

Register (Offset 0Ch) bit 0:3 -Max Link Speed. Below example:

linux-3.0.35-imx/arch/arm/mach-mx6/pcie.c 

static int __devinit imx_pcie_pltfm_prob

        usleep_range(3000, 4000);

        imx_pcie_regions_setup(dbi_base);

        usleep_range(3000, 4000);

+        /* force gen1 only */

+        tmp =readl(dbi_base + LNK_CAP) & ~0x0F;

+        writel(tmp | 0x01, dbi_base + LNK_CAP);

    /* start link up */

        imx_pcie_clrset(IOMUXC_GPR12_APP_LTSSM_ENABLE, 1 << 10,

            IOMUXC_GPR12);

Best regards

igor

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748 Views
balashanmugam
Contributor III

hi igor,

     Still we are facing the same issue, even after applying this patch too.

Regards,

Arulpandiyan Vadivel.

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igorpadykov
NXP Employee
NXP Employee

Hi Arulpandiyan

suggest to measure signal levels (eye diagram) with

AN4784 AN4784: PCIe Certification Guide for i.MX

~igor

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