IMX6 IPU - Video Capture

[vinothkumarraje]

All,

Need a clarification on IMX6 SOLO IPU programming. Our requirement is to capture video frames and dump it to the memory(CSI->SMFC->IDMAC).

To be more specific, an analog camera connected to a external decoder which connects to CSI1port as 8-bit interface. The video data format is BT656 720*480i YUV4:2:2 data.

The camera and decoder driver has been validated in different variant & works fine.

The current issue is to bring-up capture on IMX6 in QNX platform.  Referred the Linux BSP and programmed the CSI registers, still not able to see valid image on frame buffer and no status change in INT_STATUS(1 - 10) register.

Attaching the register dump taken on the target. Please review it.

Please point the debug key registers to check the state of IPU, like data get parsed on CSI register, DMA blocked in error, etc....

This table summarizes the pin details of external decoder connect to IMX6

Module LGA Pad	iMX6 Signal Name B1-Sample	Project Signal name	PAD Name
H25	IMX_CSI1_PIXCLK	DECODER_BT656_CLK	EIM_A16
G24	IMX_CSI1_DAT(12)	DECODER_BT656_D(0)	EIM_A17
J22	IMX_CSI1_DAT(13)	DECODER_BT656_D(1)	EIM_A18
G25	IMX_CSI1_DAT(14)	DECODER_BT656_D(2)	EIM_A19
H22	IMX_CSI1_DAT(15)	DECODER_BT656_D(3)	EIM_A20
H23	IMX_CSI1_DAT(16)	DECODER_BT656_D(4)	EIM_A21
F24	IMX_CSI1_DAT(17)	DECODER_BT656_D(5)	EIM_A22
J21	IMX_CSI1_DAT(18)	DECODER_BT656_D(6)	EIM_A23
F25	IMX_CSI1_DAT(19)	DECODER_BT656_D(7)	EIM_A24

PAD Mux register programming sequence

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

HW_WR_REG32(ctrl_vaddr+EIMADDR16_MUXCTRL_OFFSET, 0x00000002);

HW_WR_REG32(ctrl_vaddr+EIMADDR16_PADCTRL_OFFSET,0x0000B0B1);/*IMX_CSI1_PIXCLK*/

HW_WR_REG32(ctrl_vaddr+EIMADDR17_MUXCTRL_OFFSET,0x00000002);

HW_WR_REG32(ctrl_vaddr+EIMADDR17_PADCTRL_OFFSET,0x0000B0B1);/*IMX_CSI1_DAT(12)*/

HW_WR_REG32(ctrl_vaddr+EIMADDR18_MUXCTRL_OFFSET,0x00000002);

HW_WR_REG32(ctrl_vaddr+EIMADDR18_PADCTRL_OFFSET,0x0000B0B1);/*IMX_CSI1_DAT(13)*/

HW_WR_REG32(ctrl_vaddr+EIMADDR19_MUXCTRL_OFFSET,0x00000002);

HW_WR_REG32(ctrl_vaddr+EIMADDR19_PADCTRL_OFFSET,0x0000B0B1);/*IMX_CSI1_DAT(14)*/

HW_WR_REG32(ctrl_vaddr+EIMADDR20_MUXCTRL_OFFSET,0x00000002);

HW_WR_REG32(ctrl_vaddr+EIMADDR20_PADCTRL_OFFSET,0x0000B0B1);/*IMX_CSI1_DAT(15)*/

HW_WR_REG32(ctrl_vaddr+EIMADDR21_MUXCTRL_OFFSET,0x00000002);

HW_WR_REG32(ctrl_vaddr+EIMADDR21_PADCTRL_OFFSET,0x0000B0B1);/*IMX_CSI1_DAT(16)*/

HW_WR_REG32(ctrl_vaddr+EIMADDR22_MUXCTRL_OFFSET,0x00000002);

HW_WR_REG32(ctrl_vaddr+EIMADDR22_PADCTRL_OFFSET,0x0000B0B1);/*IMX_CSI1_DAT(17)*/

HW_WR_REG32(ctrl_vaddr+EIMADDR23_MUXCTRL_OFFSET,0x00000002);

HW_WR_REG32(ctrl_vaddr+EIMADDR23_PADCTRL_OFFSET,0x0000B0B1);/*IMX_CSI1_DAT(18)*/

HW_WR_REG32(ctrl_vaddr+EIMADDR24_MUXCTRL_OFFSET,0x00000002);

HW_WR_REG32(ctrl_vaddr+EIMADDR24_PADCTRL_OFFSET,0x0000B0B1);/*IMX_CSI1_DAT(19)*/

Regards

Vinoth

Original Attachment has been moved to: imx_ipu_reg_dump_2.txt.zip

[igorpadykov]

Hi Vinothkumar

CSI BT656 OSless example can be found in SDK, with

description in sect.18.5.2.3 BT656 mode iMX6_Firmware_Guide.pdf

i.MX 6Series Platform SDK  : Bare-metal SDK for the i.MX 6

in linux one can dump IPU/CCM registers and compare them with custom

board.

Best regards

igor

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[vinothkumarraje]

Hi Igor,

I had referred the IMX SDK firmware guide, its much useful on pointing the key registers.

Need a clarification on programming the CSI IPU_CSI1_SENS_FRM_SIZE & IPU_CSI1_ACT_FRM_SIZE register.

In our custom board, SD NTSC camera connect to the decoder and decoder programmed to send BT656, YUV4:2:2, NTSC interlaced, 720*243 fileds.

So what should be the values of SENS_FRM_SIZE & ACT_FRM_SIZE

1)

CSI1_SENS_FRM_WIDTH = (720-1);

CSI1_SENS_FRM_HEIGHT = (243-1);

CSI1_ACT_FRM_WIDTH = (720-1);

CSI1_ACT_FRM_HEIGHT = (240-1);

or

2)

CSI1_SENS_FRM_WIDTH = (720-1);

CSI1_SENS_FRM_HEIGHT = (525-1);

CSI1_ACT_FRM_WIDTH = (720-1);

CSI1_ACT_FRM_HEIGHT = (480-1);

Regards

Vinoth

[igorpadykov]

Hi Vinoth

size settings for interlaced case are the same as for non-interlaced.

~igor