IMX6 IPU Display Clock Configuration Help

[tengri]

Hi All,

I am having a trouble setting up the the clock rate of IPU1DI0 of IMX6Q. The platform is Nitrogen6_max fron BD and using the kernel version 3.14.52 with ubuntu trusty. Currently the parent clock of IPU1DI0 is set to PLL5_vid_dev (76MHz), and the clock divider being 2 (38MHz) according to clock summary result. I want to bring this IPU clock rate to a lower value, by increasing the clock divider. I am aware that the relevant value should be written to CCM_CHSCCDR (base+0x34) as per IMX6QRM, but where do I need to make the changes (in U-boot or kernel and what are the source files) ?

There is this parent clock assignment line in clk-imx6q.c :
clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider(“ipu1_di0_pre”, “ipu1_di0_pre_sel”, base + 0x34, 3, 3);

If I'm not mistaken, the imx_clk_divider should return the divider value. But here how the divisor is determined ? 

Thanks in Advance

[igorpadykov]

Hi Anuradha

PLL5 selections can be found in

linux/include/dt-bindings/clock/imx6qdl-clock.h

also please refer to generic linux clock api description in

Linux/drivers/clk/clk-divider.c - Linux Cross Reference - Free Electrons 

http://elinux.org/images/b/b8/Elc2013_Clement.pdf

Best regards
igor
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