I2C6 configuration on the SAI5_RXFS and SAI5_RXC pads on the IMX8MPLUSLPD4-EVK

[khab31]

I'd like to configure I2C6 on the SAI5_RXFS and SAI5_RXC pads on the IMX8MPLUSLPD4-EVK board.
To do this, I have configured the following registers:

/* For SDA */

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 0x00000003

IOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 0x000001E6

IOMUXC_I2C6_SDA_IN_SELECT_INPUT = 0x00000001

/* For SCL */

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 0x00000003

IOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 0x000001E6

IOMUXC_I2C6_SCL_IN_SELECT_INPUT = 0x00000001

/* Set I2C6 input clock to 66MHz*/

CCM_TARGET_ROOT_I2C6 = 0x17000001

CCM_CCGR_I2C6 = 0x00000003

When I initialize an I2C communication by following the steps below:

1- reset and enable I2C6 : I2C_I2CR = 0x0 then I2C_I2CR = I2C_I2CR_IEN

2 - make sure bus is free by reading I2SR ( (I2C_I2SR & I2C_I2SR_IBB) == 0)

3 - clear both IAL and IIF bits by writing I2SR : I2C_I2SR = 0x0

4 - assert START signal by writing I2CR : I2C_I2CR = I2C_I2CR_IEN | I2C_I2CR_MSTA | I2C_I2CR_MTX = 0xB0

5 - wait till busy after the START signal by reading I2SR :  I2SR is equal to 0x81 , the bus is not busy and i cant send slave adress.

I've applied these same configurations and steps on the I2C3 bus with I2C3_SDA and I2C3_SCL pads, and it works fine, but I can't get the I2C6 bus to work.

Are there other registers to configure for the I2C6 or other steps to perform?

[khab31]

Hi,

I come back to you for an answer to my first question.
I remind you that, I'm not working for linux OS, but I am developing for QNX OS, I am looking for the low level configuration to run the I2C6 function on SAI5_RXFS and SAI5_RXC pins.
I remind you that I have configured the following registers but it does not work:
/* For SDA*/
IOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 0x00000003
IOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 0x000001E6
IOMUXC_I2C6_SDA_IN_SELECT_INPUT = 0x00000001
/* For SCL */
IOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 0x00000003
IOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 0x000001E6
IOMUXC_I2C6_SCL_IN_SELECT_INPUT = 0x00000001
/* Set I2C6 input clock to 66MHz*/
CCM_TARGET_ROOT for I2C6 (@0x3038A500) = 0x17000001
CCM_CCGR for I2C6 (@0x30384340) = 0x00000003

Could you tell me if there are other configurations to make?

[JosephAtNXP]

Hi,

Sorry for the late reply,

I2C6 doesn't need extra configuration, should work as the other I2C interfaces work.

I'd check disabling OD enable to disable, the module itself presents the OD before the PAD, so it normally is disabled, try with 0x1c2.

Then, move to read that the changes are actually performed as you have configured them.

And keep what you have tried, the configuration is OK and the initialization is aligned with chapter 17.1.4.1 Initialization sequence from i.MX 8M Plus Reference Manual.

For further initialization steps, you could track down u-boot i2c init.

Regards,

[khab31]

Hi,

I did the test by disabling the OD with the value 0x1C2 , but it still does not work, below the values read from the registers during the test:
IOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 0x00000003
IOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 0x000001C2
IOMUXC_I2C6_SDA_IN_SELECT_INPUT = 0x00000001

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 0x00000003
IOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 0x000001C2
IOMUXC_I2C6_SCL_IN_SELECT_INPUT = 0x00000001

CCM_TARGET_ROOT for I2C6 (@0x3038A500) = 0x17000001
CCM_CCGR for I2C6 (@0x30384340) = 0x00000003

Is there another register to check?

Regards,

[khab31]

Hi,

Sorry, I don't work under Linux, my code is under QNX OS, I can't apply this proposed solution.

I would like to know which registers (in more of what I indicated) to configure directly so that the I2C6 works on the SAI5_RXFS and SAI5_RXC pins of the imx8. Are there any other registers I need to configure, or any other steps I need to take?

Regards,

[khab31]

Hi, @JosephAtNXP , 

Thank you for your reply.

I'm working on cortex A53. I'm not disabled SAI_RXFS and SAI5_RXC functions.

Should we deactivate them, and how?

[JosephAtNXP]

Hi,

Base device tree uses those pins and I linked them in the reply, you should disable the interfaces and add one i2c interface instead of your register work because linux expects to work with them.

&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
-	status = "okay";
+       status = "disabled";
};

&micfil {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pdm>;
	assigned-clocks = <&clk IMX8MP_CLK_PDM>;
	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <196608000>;
-	status = "okay";
+       status = "disabled";
};

&i2c6 {
	clock-frequency = <100000>; /* Lower clock speed for external bus. */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c6>;
	status = "okay";
};

pinctrl_i2c6: i2c6grp {
	fsl,pins = <
		MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA         0x400001c2
		MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL        0x400001c2
	>;
};

Patch the device tree like this and you should make it.

Regards,

[khab31]

Hi,

Sorry, I don't work under Linux, my code is under QNX OS, I can't apply this solution.

I would like to know which registers (in more of what I indicated) to configure directly so that the I2C6 works on the SAI5_RXFS and SAI5_RXC pins of the imx8. Are there any other registers I need to configure, or any other steps I need to take?

Regards,

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

Is your work done over cortex-A or cortex-M?

Have you disabled SAI5_RXFS and SAI5_RXC functions?

Regards