Hi,
i am working on custom board with Imx RT1176 microcontroller onboard. I am trying to establish communication between cores. My goal is for both cores to be able to read and write in shared memory. IDE is Keil, debugger Ulink2.
I started from SDK example MU communication with interrupt. It works fine.
I have read AN13264 and tried using shared memory to write from M7 and from M4.
When i use CM4 DTCM I can write and read from both cores, but when I try to write to OCRAM only M7 core can write. I can read the data from M4 side, but I cannot write.
I tried disabling bus cache like this thread posted:
but nothing changes.
What could be the reasons M4 core cannot write to OCRAM part of the shared memory?
Any help is appreciated,
Best Regards,
Milan.
Hi @Milan_Ignjatovic ,
I'm facing a similar problem, virables defined in CM4 DTCM can be read by M7, but couldn't be modified by M7(changes couldn't be detected by M4).
Would you please share the CM4 DTCM demo project? Thanks
Hi @Milan_Ignjatovic ,
Not sure how M7 core communicate with M4 on your side, but if M7 is writing to the RAM, M4 can read but not write in the same time.
Have a great day,
Kan
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Hi Kan,
i tried writing to OCRAM1, OCRAM2, OCRAM1 ECC and OCRAM2 ECC as those regions are mentioned in AN13264 as typical memory which can be used as shared memory:
OCRAM1: 0x2024_0000
OCRAM2: 0x202C_0000
OCRAM1_ECC: 0x2034_0000
OCRAM2_ECC: 0x2035_0000
Best Regards,
Milan.
Hi @Milan_Ignjatovic ,
Which OCRAM are you referring to ? Please kindly clarify.
Have a great day,
Kan
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