I.MX8MLPLUS ASRC resampling issue

[amandalin]

@hongdong_chu 

客户在用NXP I.MX8MPLUS，I.MX8MPLUS搭配外部的FPGA and DANTE 音频模块。首先I.MX8MPLUS在整个板子上面是从设备，I.MX8MPLUS通过网络1588协议跟外部的Clock generator相连后，链接到FPGA后，达到时钟同步。FPGA的MCLK通过SAI3跟I.MX8MPLS连接；外部的DANTE模块跟I.MX8MPLUS通过SAI2相连，但是DANTE的采样率不稳定（DANTE的音频模块时钟是DANTE自己的时钟）。在这个架构里，因为两个信号源分别是通过FPGA和DANTE模块给过来，时钟域不同，客户希望通过I.MX8MPLUS的ASRC达到DANTE和I.MX8MPLUS的时钟域一样，客户想了解ASRC工作原理以及是否满足他们现在架构要求

谢谢

[hongdong_chu]

@amandalin 

As discussed in the meeting with Hollyland, the ASRC can indeed address sample rate mismatches between different clock domains, but there are still some issues.

In the customer’s system diagram, there is already a synchronization mechanism in place among the FPGA, the i.MX8MP, and the network side. The remaining challenge is the synchronization with DANTE.

The ASRC can align the DANTE clock rate to its internal operating clock, but the operating clock is derived from the SYS PLL, which uses the 24 MHz crystal as clock source by default. Therefore, the ASRC operating clock and the network‑based clock still have a rate matching problem. And changing the SYS PLL's reference clock may affect the stability of the whole system, so the problem is difficult to address.

One feasible solution is to use an external module for the ASRC conversion, with its clock sourced from the clock generator in the diagram.

[amandalin]

@hongdong_chu 

many  thanks for you help ,customer had accepted us suggest ,he will choose add more IC to solution it.

thanks a lot