I.MX8 SCU scfw link GPIO interrupt to Interrupt handler

[fd9750]

Hi,

I am experimenting with an IMX8QM MEK board in order to finally make our own board.

For that own board we would ultimately like to use GPIO0 pin 5 as an interrupt pin to trigger various actions. Using the scfw porting guide I have created the following two snippets of code:

This section of code should initialize the pin and set it up to generate the interrupts:

        GPIO_config.direction = kGPIO_DigitalInput;

        GPIO_config.outputLogic=0; /*!< Set a default output logic, which has no use in input */

        GPIO_config.interruptMode=kGPIO_IntLowLevel;

        GPIO_PinInit((GPIO_Type *)GPIO0_BASE, 5U, &GPIO_config);

        GPIO_EnableInterrupts((GPIO_Type *)GPIO0_BASE, PIN5_MASK);

This is the initial IRQHandler I would like to test

        void GPIO0_PIN5_IRQHandler (void)

        {

            GPIO_ClearPinsInterruptFlags((GPIO_Type *)GPIO0_BASE, PIN5_MASK);

        }

Both snippets of code reside in the experimental board.c file and build without problems so I assume they are OK.

What I am unable to find is how to link the target IRQHandler to the actual interrupt. There are a few other IRQHandlers in the board.c code but neither the source code nor the scfw_port.pdf file provide any info as to how those IRQHandlers were linked to their respective interrupt sources.

Does anyone have some more info on this or a link to where I could find the necessary information?

Any help on this would be very much appreciated.

[fd9750]

Hi Qmiller,

I very much thought that what you describe is exactly what the existing scfw code does, I did not know exactly in which file it was done but now I do.

In the mean time I have doing some further digging and I think I have found a possible solution but I am missing an essential bit of information. When the provided functions to set up the GPIO interrupt ( as documented in the scfw_port.pdf document ) are used they must ultimately link the GPIO interrupt to one of the INTMUX_n or IOMIX_n units which in their turn link to an NVIC_number. Which GPIO links to which MUX unit is unfortunately not documented.

If we can find which MUX unit GPIO5 is linked to it should be possible to assign a vector to the NVIC table using the NVIC_SetVector (127, (uint32_t)GPIO0_PIN5_IRQHandler) function to define the IRQ handler's address. The number 127 I have picked is just an "educated guess" number I used to check whether or not the NVIC_SetVector function actually compiles and builds, which it does.

If we could get any additional info on the GPIO/MUX linking I think we can make it work or at least do some testing/debugging.

[Zhiming_Liu]

You can find other handler in startup_MX8QM.o, this file is compiled from startup_MX8QM.S which we don't release it to customer. This means you can't add your handler.

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