I.MX7 LPDDR3 DQ swap in the byte

[frankyhsu]

Hi

We are refer to i.MX7 7D LPDDR3 CPU VAL BOARD design. In the LPDDR3 page, we see the DQx are swapped in its own byte group. Is there any rule needing to follow or we can swap any location we want in the byte? I can not see a rule in the connection of the EVK schematic. The only rule seems to be the byte need to have the corresponding strobe, is it?

Thanks.

[igorpadykov · Accepted solution]

Hi Franky

you are right, for lpddr3 only rule that byte need to have the corresponding strobe,

for ddr3 some swap restrictions were imposed by “Write Leveling” section in JESD79-3E.

Best regards
igor
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