I.MX6UL does not boot from SD

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I.MX6UL does not boot from SD

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Contributor III

On our custom board we can boot the system from QSPI Flash without problem.

However, it does not boot from SD. Under U-Boot and Linux the SD card works without problems

when we boot from QSPI initially.

Thus, the hardware seems OK.

=> mmc dev 1
switch to partitions #0, OK
mmc1 is current device
=> mmc info
Device: FSL_SDHC
Manufacturer ID: 3
OEM: 5344
Name: SU08G
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 7.4 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
=>

We have the same configuration like on IMX6UL development kit.

Also, in QSPI mode on the custom board I can read 0x812 from SRC Boot Mode Register

=> md 20d8004 1
020d8004: 00000812 ....

And it matches exactly CONFIGURATIONs we have on the dev kit.

There is only one difference. The dev kit boots from the SD card.

SBC_SBMR1 shows 0x852 in that case on devkit.. And this bit maps to CFG16. 

However, when I apply  a high level signal to CFG16 the board does not boot from SD.

After power on I can see slow activity on SD2_CLK, then fast activity. It seems the board recognizes the card.

And probably starts booting. But then it fails.

Everything points to the problems with ROM Boot Loader.

Please let me know if there is some idea related to that issue.

Thanks in advance

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NXP TechSupport
NXP TechSupport

Hello,

  Please create request in order to get boot utility for further analyzing.

Support|NXP 

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
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Contributor III

Hi Yuri,

I have compiled the latest U-boot  and everything started to work on both the boards ( custom and devkit).

git clone http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git

cd uboot-imx
git checkout -b imx_v2017.03_4.9.11_1.0.0_ga origin/imx_v2017.03_4.9.11_1.0.0_ga

make imx6ul_14x14_evk_defconfig

make

sudo dd if=u-boot-dtb.imx of=/dev/sdb bs=512 seek=2

Note, I did not apply any new calibration settings. I juts compiled u-boot as it is.

Anyway I need to calibrate the custom board.

Thus, I could get the calibration log on the custom board.

U-Boot 2017.03-00001-ga2fea67 (Oct 18 2017 - 17:37:04 -0500)

CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 43C
Reset cause: POR
Model: Freescale i.MX6 UltraLite 14x14 EVK Board
Board: MX6UL 14x14 EVK
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Display: TFT43AB (480x272)
Video: 480x272x24
In: serial
Out: serial
Err: serial
switch to partitions #0, OK
mmc1 is current device
Net: No ethernet found.
Normal Boot
Hit any key to stop autoboot: 0
=> mmc dev 1
switch to partitions #0, OK
mmc1 is current device
=> dcache off
=> icache off
=> fatload mmc 1:1 0x00907000 ddr-test-uboot-jtag-mx6ul.bin
reading ddr-test-uboot-jtag-mx6ul.bin
66348 bytes read in 28 ms (2.3 MiB/s)
=> go 0x00907000
## Starting application at 0x00907000 ...

============================================
DDR Stress Test (2.6.0)
Build: Aug 1 2017, 17:38:34
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 UltraLite(0x64)
Internal Revision = TO1.2
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000852
SRC_SBMR2(0x020d801c) = 0x02000041
============================================

What ARM core speed would you like to run?
Type 1 for 200MHz, 2 for 400MHz, 3 for 528MHz, 4 for 700MHz
ARM Clock set to 528MHz

============================================
DDR configuration
DDR type is DDR3
Data width: 16, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 512MB
============================================

Current Temperature: 48
============================================

Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB
DDR density selected (MB): 512

Would do you want to change VDD_SOC_CAP/VDD_ARM_CAP voltage? Type 'y' to run and 'n' to skip

Would do you want run DDR Calibration? Type 'y' to run and 'n' to skip

Calibration will run at DDR frequency 400MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
Please enter the MR1 value on the initilization script
This will be re-programmed into MR1 after write leveling calibration
Enter as a 4-digit HEX value, example 0004, then hit enter
0004DDR Freq: 396 MHz

ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00000000
Write DQS delay result:
Write DQS0 delay: 0/256 CK
Write DQS1 delay: 0/256 CK

Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x00000011
. HC_DEL=0x00000001 result[01]=0x00000000
. HC_DEL=0x00000002 result[02]=0x00000000
. HC_DEL=0x00000003 result[03]=0x00000011
. HC_DEL=0x00000004 result[04]=0x00000011
. HC_DEL=0x00000005 result[05]=0x00000011
. HC_DEL=0x00000006 result[06]=0x00000011
. HC_DEL=0x00000007 result[07]=0x00000011
. HC_DEL=0x00000008 result[08]=0x00000011
. HC_DEL=0x00000009 result[09]=0x00000011
. HC_DEL=0x0000000A result[0A]=0x00000011
. HC_DEL=0x0000000B result[0B]=0x00000011
. HC_DEL=0x0000000C result[0C]=0x00000011
. HC_DEL=0x0000000D result[0D]=0x00000011
DQS HC delay value low1 = 0x00000101, high1=0x00000202
loop ABS offset to get HW_DG_LOW
. ABS_OFFSET=0x00000000 result[00]=0x00000011
. ABS_OFFSET=0x00000004 result[01]=0x00000011
. ABS_OFFSET=0x00000008 result[02]=0x00000011
. ABS_OFFSET=0x0000000C result[03]=0x00000011
. ABS_OFFSET=0x00000010 result[04]=0x00000011
. ABS_OFFSET=0x00000014 result[05]=0x00000010
. ABS_OFFSET=0x00000018 result[06]=0x00000010
. ABS_OFFSET=0x0000001C result[07]=0x00000000
. ABS_OFFSET=0x00000020 result[08]=0x00000000
. ABS_OFFSET=0x00000024 result[09]=0x00000000
. ABS_OFFSET=0x00000028 result[0A]=0x00000000
. ABS_OFFSET=0x0000002C result[0B]=0x00000000
. ABS_OFFSET=0x00000030 result[0C]=0x00000000
. ABS_OFFSET=0x00000034 result[0D]=0x00000000
. ABS_OFFSET=0x00000038 result[0E]=0x00000000
. ABS_OFFSET=0x0000003C result[0F]=0x00000000
. ABS_OFFSET=0x00000040 result[10]=0x00000000
. ABS_OFFSET=0x00000044 result[11]=0x00000000
. ABS_OFFSET=0x00000048 result[12]=0x00000000
. ABS_OFFSET=0x0000004C result[13]=0x00000000
. ABS_OFFSET=0x00000050 result[14]=0x00000000
. ABS_OFFSET=0x00000054 result[15]=0x00000000
. ABS_OFFSET=0x00000058 result[16]=0x00000000
. ABS_OFFSET=0x0000005C result[17]=0x00000000
. ABS_OFFSET=0x00000060 result[18]=0x00000000
. ABS_OFFSET=0x00000064 result[19]=0x00000000
. ABS_OFFSET=0x00000068 result[1A]=0x00000000
. ABS_OFFSET=0x0000006C result[1B]=0x00000000
. ABS_OFFSET=0x00000070 result[1C]=0x00000000
. ABS_OFFSET=0x00000074 result[1D]=0x00000000
. ABS_OFFSET=0x00000078 result[1E]=0x00000000
. ABS_OFFSET=0x0000007C result[1F]=0x00000000

loop ABS offset to get HW_DG_HIGH
. ABS_OFFSET=0x00000000 result[00]=0x00000000
. ABS_OFFSET=0x00000004 result[01]=0x00000000
. ABS_OFFSET=0x00000008 result[02]=0x00000000
. ABS_OFFSET=0x0000000C result[03]=0x00000000
. ABS_OFFSET=0x00000010 result[04]=0x00000000
. ABS_OFFSET=0x00000014 result[05]=0x00000000
. ABS_OFFSET=0x00000018 result[06]=0x00000000
. ABS_OFFSET=0x0000001C result[07]=0x00000000
. ABS_OFFSET=0x00000020 result[08]=0x00000000
. ABS_OFFSET=0x00000024 result[09]=0x00000011
. ABS_OFFSET=0x00000028 result[0A]=0x00000000
. ABS_OFFSET=0x0000002C result[0B]=0x00000000
. ABS_OFFSET=0x00000030 result[0C]=0x00000000
. ABS_OFFSET=0x00000034 result[0D]=0x00000000
. ABS_OFFSET=0x00000038 result[0E]=0x00000000
. ABS_OFFSET=0x0000003C result[0F]=0x00000000
. ABS_OFFSET=0x00000040 result[10]=0x00000000
. ABS_OFFSET=0x00000044 result[11]=0x00000011
. ABS_OFFSET=0x00000048 result[12]=0x00000001
. ABS_OFFSET=0x0000004C result[13]=0x00000001
. ABS_OFFSET=0x00000050 result[14]=0x00000011
. ABS_OFFSET=0x00000054 result[15]=0x00000011
. ABS_OFFSET=0x00000058 result[16]=0x00000011
. ABS_OFFSET=0x0000005C result[17]=0x00000011
. ABS_OFFSET=0x00000060 result[18]=0x00000011
. ABS_OFFSET=0x00000064 result[19]=0x00000011
. ABS_OFFSET=0x00000068 result[1A]=0x00000011
. ABS_OFFSET=0x0000006C result[1B]=0x00000011
. ABS_OFFSET=0x00000070 result[1C]=0x00000011
. ABS_OFFSET=0x00000074 result[1D]=0x00000011
. ABS_OFFSET=0x00000078 result[1E]=0x00000011
. ABS_OFFSET=0x0000007C result[1F]=0x00000011


BYTE 0:
Start: HC=0x00 ABS=0x14
End: HC=0x02 ABS=0x20
Mean: HC=0x01 ABS=0x1A
End-0.5*tCK: HC=0x01 ABS=0x20
Final: HC=0x01 ABS=0x20
BYTE 1:
Start: HC=0x00 ABS=0x1C
End: HC=0x02 ABS=0x20
Mean: HC=0x01 ABS=0x1E
End-0.5*tCK: HC=0x01 ABS=0x20
Final: HC=0x01 ABS=0x20

DQS calibration MMDC0 MPDGCTRL0 = 0x41200120, MPDGCTRL1 = 0x00000000

Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 01:byte 0 fail.
result 11:byte 0, 1 fail.
Starting Read calibration...

ABS_OFFSET=0x00000000 result[00]=0x11
ABS_OFFSET=0x04040404 result[01]=0x11
ABS_OFFSET=0x08080808 result[02]=0x11
ABS_OFFSET=0x0C0C0C0C result[03]=0x11
ABS_OFFSET=0x10101010 result[04]=0x11
ABS_OFFSET=0x14141414 result[05]=0x11
ABS_OFFSET=0x18181818 result[06]=0x11
ABS_OFFSET=0x1C1C1C1C result[07]=0x00
ABS_OFFSET=0x20202020 result[08]=0x00
ABS_OFFSET=0x24242424 result[09]=0x00
ABS_OFFSET=0x28282828 result[0A]=0x00
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00
ABS_OFFSET=0x30303030 result[0C]=0x00
ABS_OFFSET=0x34343434 result[0D]=0x00
ABS_OFFSET=0x38383838 result[0E]=0x00
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00
ABS_OFFSET=0x40404040 result[10]=0x00
ABS_OFFSET=0x44444444 result[11]=0x00
ABS_OFFSET=0x48484848 result[12]=0x00
ABS_OFFSET=0x4C4C4C4C result[13]=0x00
ABS_OFFSET=0x50505050 result[14]=0x00
ABS_OFFSET=0x54545454 result[15]=0x00
ABS_OFFSET=0x58585858 result[16]=0x00
ABS_OFFSET=0x5C5C5C5C result[17]=0x00
ABS_OFFSET=0x60606060 result[18]=0x00
ABS_OFFSET=0x64646464 result[19]=0x00
ABS_OFFSET=0x68686868 result[1A]=0x00
ABS_OFFSET=0x6C6C6C6C result[1B]=0x01
ABS_OFFSET=0x70707070 result[1C]=0x01
ABS_OFFSET=0x74747474 result[1D]=0x11
ABS_OFFSET=0x78787878 result[1E]=0x11
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11

Byte 0: (0x1c - 0x68), middle value:0x42
Byte 1: (0x1c - 0x70), middle value:0x46
MMDC0 MPRDDLCTL = 0x40404642
Starting Write calibration...

ABS_OFFSET=0x00000000 result[00]=0x11
ABS_OFFSET=0x04040404 result[01]=0x11
ABS_OFFSET=0x08080808 result[02]=0x11
ABS_OFFSET=0x0C0C0C0C result[03]=0x11
ABS_OFFSET=0x10101010 result[04]=0x11
ABS_OFFSET=0x14141414 result[05]=0x11
ABS_OFFSET=0x18181818 result[06]=0x11
ABS_OFFSET=0x1C1C1C1C result[07]=0x11
ABS_OFFSET=0x20202020 result[08]=0x11
ABS_OFFSET=0x24242424 result[09]=0x10
ABS_OFFSET=0x28282828 result[0A]=0x10
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00
ABS_OFFSET=0x30303030 result[0C]=0x00
ABS_OFFSET=0x34343434 result[0D]=0x00
ABS_OFFSET=0x38383838 result[0E]=0x00
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00
ABS_OFFSET=0x40404040 result[10]=0x00
ABS_OFFSET=0x44444444 result[11]=0x00
ABS_OFFSET=0x48484848 result[12]=0x00
ABS_OFFSET=0x4C4C4C4C result[13]=0x00
ABS_OFFSET=0x50505050 result[14]=0x00
ABS_OFFSET=0x54545454 result[15]=0x00
ABS_OFFSET=0x58585858 result[16]=0x00
ABS_OFFSET=0x5C5C5C5C result[17]=0x00
ABS_OFFSET=0x60606060 result[18]=0x00
ABS_OFFSET=0x64646464 result[19]=0x00
ABS_OFFSET=0x68686868 result[1A]=0x00
ABS_OFFSET=0x6C6C6C6C result[1B]=0x00
ABS_OFFSET=0x70707070 result[1C]=0x00
ABS_OFFSET=0x74747474 result[1D]=0x00
ABS_OFFSET=0x78787878 result[1E]=0x00
ABS_OFFSET=0x7C7C7C7C result[1F]=0x00

Byte 0: (0x24 - 0x7c), middle value:0x50
Byte 1: (0x2c - 0x7c), middle value:0x54

MMDC0 MPWRDLCTL = 0x40405450


MMDC registers updated from calibration

Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00000000

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x41200120
MPDGCTRL1 PHY0 (0x021b0840) = 0x00000000

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x40404642

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x40405450


Success: DDR calibration completed!!!

The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same value
Would do you want run DDR Stress Test? Type 'y' to run and 'n' to skip

Enter desired START freq (135 to 672 MHz), then hit enter.
Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.
400
The freq you entered was: 400

Enter desired END freq (135 to 672 MHz), then hit enter.
Make sure this is equal to or greater than start freq
400
The freq you entered was: 400

Do you want to run DDR Stress Test for simple loop or Over Night Test?
Type '0' for simple loop. Type '1' for Over Night Test

DDR Stress Test Iteration 1
Current Temperature: 49
============================================

DDR Freq: 396 MHz
t0.1: data is addr test
t0: memcpy11 SSN test
t1: memcpy8 SSN test
t2: byte-wise SSN test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Stress Test is complete!

Do you have any instruction how to apply the obtained calibration info to imximage.cfg which looks different ?

As far as I understand it is necessary to change few coefficients that come from a calibration log.

Please specify which ones

DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff

DATA 4 0x020E04B4 0x000C0000
DATA 4 0x020E04AC 0x00000000
DATA 4 0x020E027C 0x00000030
DATA 4 0x020E0250 0x00000030
DATA 4 0x020E024C 0x00000030
DATA 4 0x020E0490 0x00000030
DATA 4 0x020E0288 0x00000030
DATA 4 0x020E0270 0x00000000
DATA 4 0x020E0260 0x00000030
DATA 4 0x020E0264 0x00000030
DATA 4 0x020E04A0 0x00000030
DATA 4 0x020E0494 0x00020000
DATA 4 0x020E0280 0x00000030
DATA 4 0x020E0284 0x00000030
DATA 4 0x020E04B0 0x00020000
DATA 4 0x020E0498 0x00000030
DATA 4 0x020E04A4 0x00000030
DATA 4 0x020E0244 0x00000030
DATA 4 0x020E0248 0x00000030
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B0800 0xA1390003
DATA 4 0x021B080C 0x00000000
DATA 4 0x021B083C 0x41490145
DATA 4 0x021B0848 0x40404546
DATA 4 0x021B0850 0x4040524D
DATA 4 0x021B081C 0x33333333
DATA 4 0x021B0820 0x33333333
DATA 4 0x021B082C 0xf3333333
DATA 4 0x021B0830 0xf3333333
DATA 4 0x021B08C0 0x00921012
DATA 4 0x021B08b8 0x00000800
DATA 4 0x021B0004 0x0002002D
DATA 4 0x021B0008 0x00333030
DATA 4 0x021B000C 0x676B52F3
DATA 4 0x021B0010 0xB66D8B63
DATA 4 0x021B0014 0x01FF00DB
DATA 4 0x021B0018 0x00201740
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B002C 0x000026D2
DATA 4 0x021B0030 0x006B1023
DATA 4 0x021B0040 0x0000004F
DATA 4 0x021B0000 0x84180000
DATA 4 0x021B001C 0x02008032
DATA 4 0x021B001C 0x00008033
DATA 4 0x021B001C 0x00048031
DATA 4 0x021B001C 0x15208030
DATA 4 0x021B001C 0x04008040
DATA 4 0x021B0020 0x00000800
DATA 4 0x021B0818 0x00000227
DATA 4 0x021B0004 0x0002552D
DATA 4 0x021B0404 0x00011006
DATA 4 0x021B001C 0x00000000

Thanks

Vitaliy

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NXP TechSupport
NXP TechSupport

Hello,

  According to the calibration log:
 

Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00000000

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x41200120
MPDGCTRL1 PHY0 (0x021b0840) = 0x00000000

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x40404642

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x40405450

  The marked as  bold present address and data to write there.

Find corresponding lines in the DCD table and modify them if needed.

Then it is needed to rebuild U-boot.

Regards,

Yuri.

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Contributor III

Hello,

I have updated only the following registers 

0x021B080C , 0x021B083C, 0x021B0848,0x021B0850

It seems  MPDGCTRL1 PHY0 (0x021b0840) is not present in imx6ull DDR controller

21B_083C MMDC PHY Read DQS Gating Control Register 0 (MMDC_MPDGCTRL0)
21B_0844 MMDC PHY Read DQS Gating delay-line Status Register (MMDC_MPDGDLST0)

Anyway everything works on our custom board.

Thanks for the help

Best regards,

Vitaliy

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NXP Employee
NXP Employee

Hello Vitaliy,

just to clarify, 6ULL has only 16 bit bus width for the DDR - Byte 0 and Byte 1. MPDGCTRL1 PHY0 stores the calibration values for Byte 2 and Byte 3 used in wider bus widths on other SoCs. Therefore this value has no meaning for 6ULL and should be ignored.

Best Regards,

Jan

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Contributor III

Hello Jan,

thanks for explanations

Best regards,

Vitaliy

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