Hi Weidong,
Unfortunately the codec we are using only supports slave mode, so setting it in master isn't an option. I updated my original question explicitly state this. Our design requires an external master clock for performance reasons so that can't be changed either.
Also, CLK1_N and CLK1_P (also refereed to as CLK1N, CLK1P, AUX clk1, and XTAL_OSC_CLK1_P/N in various Freescale documentation) (balls AC23 and AD23) can be used as inputs. I was unable to find the section in the data sheet or reference manual that you are referring to, but section 3.1 (Special Signal Considerations) of the data sheet (page 15) states that CLK1P/N can be used as either an input or output. Also, Chapter 55.2 of the reference manual (Crystal Oscillators - External Signals), shows CLK1_N and CLK1_P as IO. Finally, Chapter 15.7.5 (Clock Controller Module - Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn)) shows that you can set the Aaudio PLL (PLL4) into PLL bypass using bit 16 (BYPASS) and select CLK1_N / CLK1_P as the source (BYPASS_CLK_SRC). From looking at the IMX6SL clock driver in the Linux kernel, it's seen that all the proper muxes and clocks are implemented to achieve my goal.
It's clear to me that what I want to do is possible, and I would know how to do it in a bare metal design. My problem comes with understanding how to do this within the context of the common clock framework of the Linux kernel and the device tree. I have actually managed to get the SSI1 root clock to derive from the CLK1 source by setting various parameters for the muxes and dividers in the CCM device tree entry using the assigned-clocks, assigned-clock-parents, assigned-clock-rates parameters. I'm not sure that this is the right way to do this, and would appreciate any further guidance about best practice for setting clocks with device tree or from the driver level.
Either way, thank you for taking the time to look into this an reply.
Best,
~Matt
