Hi community,
Our partner have a question about i.MX6 EIM.
Actually, they want to access to a 8 bit external "big endian" device via EIM.
I found i.MX6 EIM supports it and chapter 22.5.19 in IMX6DQRM (Rev.1) seems explanation of this support.
However, I did not find how to set the endianness in EIM registers.
So would you let me know how to set EIM endianness to big endian?
Best Regards,
Satoshi Shimoda
解決済! 解決策の投稿を見る。
According to section 1.5.3 (Endianness Support) of the i.MX6 DQ Reference Manual :
"i.MX 6Dual/6Quad supports Little Endian mode only".
For i.MX6 S / DL : from section 1.5.3 (Endianness Support) of the RM :
"i.MX 6Solo/6DualLite supports Little Endian mode only".
The problem relates to internal peripheral modules / controllers of the i.MX6.
The ARM core in itself can be configured for Little or Big endian (please refer to ARM docs),
but this means all data, passing through the ARM core will be affected. Users often need to
use different endian modes for different (internal) peripheral modules of the SOC. The EIM
as separate IP can support Big /Little Endian, as stated in features section, but being
embedded to i.MX6 - does not.
Have a great day,
Yuri
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According to section 1.5.3 (Endianness Support) of the i.MX6 DQ Reference Manual :
"i.MX 6Dual/6Quad supports Little Endian mode only".
For i.MX6 S / DL : from section 1.5.3 (Endianness Support) of the RM :
"i.MX 6Solo/6DualLite supports Little Endian mode only".
The problem relates to internal peripheral modules / controllers of the i.MX6.
The ARM core in itself can be configured for Little or Big endian (please refer to ARM docs),
but this means all data, passing through the ARM core will be affected. Users often need to
use different endian modes for different (internal) peripheral modules of the SOC. The EIM
as separate IP can support Big /Little Endian, as stated in features section, but being
embedded to i.MX6 - does not.
Have a great day,
Yuri
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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