How to set TAMPER pins as GPIO whose properties are equal to device tree.

[shaot]

Hi, I am confused how can I set TAMPER pins as GPIO whose properties are equal to device tree.

I use imx6ull board.

I directly accessed register address with memtool and got following information.

SW_MUX_CTL_PAD_SNVS_TAMPER1: reg val 0x0

SW_PAD_CTL_PAD_SNVS_TAMPER1: reg val 0x0

other tamper pins are the same as above.

However I defined these pins for GPIO in device tree as follows.

&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
imx6ul-evk {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <

MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000110B0
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0000B0A0
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x000110B0
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x000110B0
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x000110B0
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x000110B0

The values of device tree do not set in the register.

The IMX6ULRM says that TAMPER_PIN_DISABLE in fuse has to be 11 to disable TAMPER0-9 and use as GPIO.

So I checked 0x430[21:20] and got 11. I think this means tamper pins are set as ALT5 GPIO mode.

I checked fuse in uboot too (refer to mx6ul tamper pin to gpio  ). The result is following.

Hit any key to stop autoboot: 0
=> fuse read 0 3
Reading bank 0:

Word 0x00000003: 71300070

note that 0x71300070 = 1110001001100000000000001110000

From the beggining, TAMPER_PIN_DISABLE is 11. Can I set them in device tree? I could not find any definition of tamper pins.

I could export these tamper pins in sysfs, but the values cannot be written even if I set them as output direction.

The values are always HIGH.

Why can't I set register values as defined in device tree ?

Why can't I change H/L even if I set tamper pins as output direction?

[igorpadykov]

Hi Hirotoshi

please look at imx6ull-14x14-evk.dts example, using &iomuxc_snvs..

linux-imx.git - i.MX Linux Kernel 

in latest Linux 4.9.11_1.0.0 BSP, description on link

https://www.nxp.com/webapp/Download?colCode=L4.9.11_1.0.0_LINUX_DOCS 

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[shaot]

Thank you for your reply.

I found that I defined MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000110B0 though I use imx6ULL.

So I defined in imx6ull-var-dart.dtsi as follows and removed the description of  MX6UL_PAD_SNVS_TAMPER...

&iomuxc_snvs {
pinctrl-names = "default_snvs";
pinctrl-0 = <&pinctrl_hog_2>;
imx6ul-evk {
pinctrl_hog_2: hoggrp-2 {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000110B0
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0000B0A0
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x000110B0
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x000110B0
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x000110B0
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x000110B0
>;
};
};
};

It seems to work as GPIO because H/L can be changed by sysfs.

Next, I would like to check the register value.

iomuxc_snvs is defined as follows:

iomuxc_snvs: iomuxc-snvs@02290000 {
compatible = "fsl,imx6ull-iomuxc-snvs";
reg = <0x02290000 0x10000>;
};

So the base address is 0x2290000.

/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0
#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0

From above, MX6ULL_PAD_SNVS_TAMPER1 address is 0x2290000 + 0x000C = 0x229000C.

So I checked with /unit_tests/memtool. However I could not access the register.

The result is 

root@imx6ul-var-dart:/unit_tests# ./memtool 229000c 1
E
Reading 0x1 count starting at addUnhandled fault: external abort on non-linefetch (0x1008) at 0x76faf00c
pgd = 885d0000
[76faf00c] *pgd=885f4831, *pte=02290703, *ppte=02290e33
ress 0x0229000C

Bus error

What is the problem? The addrss I accessed is wrong?

What is the register address of imx6ull not imx6ul?

[igorpadykov]

Hi Hirotoshi

for addresses please check Chapter 33 IOMUX Controller (IOMUXC)
i.MX6ULL Reference Manual
http://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf

Best regards
igor

[joseluiszabalza]

Hello igor

I have the same problem and i don't understand the answer.

Why memtool can't access to 229000c address?