How to read MIPI D Phy Register

[milav_soni]

Hello Guys,

I need to read the following MIPI D PHY Register value.

I do not find any offset of these registers in the software source.

Can you please help me out with this problem?

Thank you

[hhami_2040]

Hello All,
We have a MIPI CSI Camera OV5640 and  Imx8!!
I’m looking into checking the state of the Imx8 MIPI CSI Registers when I run gstreamer pipeline at userspace:

gst-launch-1.0 v4l2src device='/dev/video0' ! video/x-raw,format=YUY2,width=1920,height=1080,framerate=30/1 ! waylandsink -v

Is there a standard command(s) to find out MIPI CSI status register?

I want to check MIPI status register at runtime userpace, such as:
a. ECC and CRC Error Status Register
b. IRQ Status Register
c. ErrSot HS Status Register
d. ErrSotSync HS Status Register
e. ErrEsc Status Register
f. ErrSyncEsc Status Register
g. ErrControl Status Register

Can you please guide me?
Thank you in advance.

[zohargolan]

Hi @hhami_2040 ,

I have a similar problem now that I tried to get the information on the inside of the MIPI dphy . Did you ever figure out how to get this information from the command line?

Thank you for your help

Zohar

[joanxie]

if you need set PMS, pls refer to the DSI_PLLCTRL register which located at 0x32E10094

S: Bit 1-3 

M : bit 4-13

P : bit 14-19

and you can refer to the driver about this register

"https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=lf-5.1...

#define PLLCTRL_SET_PMS(x)               REG_PUT(x, 19,  1)

pllctrl |= PLLCTRL_SET_PMS(dsim->pms) | PLLCTRL_PLLEN;

dsim_write(dsim, pllctrl, DSIM_PLLCTRL);

[milav_soni]

Hello @joanxie ,

I need to read the MIPI_DPHY memory map register value (section 13.7.10 in i.MX 8M Nano Application Processor Ref. Manual Rev. 1, 11/2020)which is 64bits in width.

• Master PLL PMS Value setting Register
  (MIPI_DPHY_M_PLLPMS)
• Master PLL Control Register (MIPI_DPHY_M_PLLCTL)
• Master and Slave DPHY Control Register
  (MIPI_DPHY_B_DPHYCTL)
• Master and Slave DPHY Control Register
  (MIPI_DPHY_M_DPHYCTL)
• Master and Slave DPHY Control Register
  (MIPI_DPHY_S_DPHYCTL)

can you please tell me which of the above registers are located in which offset of the memory map?

Thank you in advance.

[joanxie]

current bsp doesn't use these registers, and you can check the latest i.mx8mp reference manual, which remove these registers already, imx8mn should be updated in the newer reference manual, so I couldn't tell the address of these registers

[milav_soni]

Hello @joanxie ,

Thank You for your reply.

So how i can verify, whether MIPI D Phy is working fine or not?

Because I am getting zero value in the "MIPI_CSIS_FRAME_COUNTER_CH0" register when 5MP Image capture.

So where is the problem? please help me out with this problem.

Thank You

[joanxie]

you can dump csi registers to check one by one and check the logfile, your information is too limited to know the issue