How to lock display interface clock (DISP_CLK) to incoming camera interface (CSI) clock ?

[ottob]

Hi There, We are interested in using the imx6 to add an overlay to a video stream. Video would come in on the parallel CSI port and go out through the parallel "Raw LCD" / Pixelport interface.  To do that properly we would like to have the input and output video clocks locked. Is that possible on the imx6? Thanks, /Otto

[igorpadykov]

Hi Otto

I am afraid this is not possible. Though IPU has external sync/clock signals,

depicted on Figure 37-39. DI's block diagram IMX6DQRM as EXT_VSYNC,EXT_CLK,

these signals are not routed externally.  EXT_CLK is connected internally as shows

Table 18-3 : ipp_di_ _ext_clk connected to ipu_di_clk_root.

Best regards

igor

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[ottob]

Ok, I appreciate the fast response Igor ! Thanks

Btw, any other customers asking for this ? Is there any chance this might be added in a later chip revision ?

[igorpadykov]

Hi Otto

this will require complete redesign, so new processor

should be produced. New chip revision can just fix

existing errata.

~igor

[ottob]

Ok, I wont be holding by breath then