How to initialize IMX6 using JLink

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How to initialize IMX6 using JLink

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davidziv
Contributor II

Hello.

I'm using IMX6 SOLO, I'm trying to write to Spansion (S25FL512SAGBHIC10) SPI NOR Using JLink.
1. Which registers needed to be initialized on IMX6 before starting the process (EIM config, clocks etc...)
2. Which memory address should I use to copy the content to? (0x8080000)

I don't have access to USB OTG, so the mfg tool is not relevant.

I'll appreciate any assistance.

David.

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davidziv
Contributor II

OK, found the right configuration for running U-BOOT from RAM

target remote localhost:2331

#monitor endian little

#monitor device MCIMX6S5

#monitor speed auto

monitor reset

monitor halt

monitor sleep 1000

#=============================================================================

# Disable WDOG

#=============================================================================

monitor memU32 0x020bc000 = 0x30

#=============================================================================

# Enable all clocks (they are disabled by ROM code)

#=============================================================================

monitor memU32 0x020c4068 = 0x00C03F3F

monitor memU32 0x020c406c = 0x0030FC03

monitor memU32 0x020c4070 = 0x0FFFC000

monitor memU32 0x020c4074 = 0x3FF00000

monitor memU32 0x020c4078 = 0x00FFF300

monitor memU32 0x020c407c = 0x0F0000C3

monitor memU32 0x020c4080 = 0x000003FF

#GPU and VPU not needed for boot

#monitor memU32 0x020c4084 = 0xffffffff

#=============================================================================

# IOMUX

#=============================================================================

#DDR IO TYPE:

monitor memU32 0x020e0774 = 0x000C0000 # IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE

monitor memU32 0x020e0754 = 0x00000000 # IOMUXC_SW_PAD_CTL_GRP_DDRPKE

#CLOCK:

monitor memU32 0x020e04ac = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0

monitor memU32 0x020e04b0 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1

#ADDRESS:

monitor memU32 0x020e0464 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS

monitor memU32 0x020e0490 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS

monitor memU32 0x020e074c = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_ADDDS

#Control:

monitor memU32 0x020e0494 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET

monitor memU32 0x020e04a0 = 0x00000000 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS

monitor memU32 0x020e04b4 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0

monitor memU32 0x020e04b8 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1

monitor memU32 0x020e076c = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_CTLDS

#Data Strobes:

monitor memU32 0x020e0750 = 0x00020000 # IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL

monitor memU32 0x020e04bc = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0

monitor memU32 0x020e04c0 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1

monitor memU32 0x020e04c4 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2

monitor memU32 0x020e04c8 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3

#Data:

monitor memU32 0x020e0760 = 0x00020000 # IOMUXC_SW_PAD_CTL_GRP_DDRMODE

monitor memU32 0x020e0764 = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B0DS

monitor memU32 0x020e0770 = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B1DS

monitor memU32 0x020e0778 = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B2DS

monitor memU32 0x020e077c = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B3DS

monitor memU32 0x020e0470 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0

monitor memU32 0x020e0474 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1

monitor memU32 0x020e0478 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2

monitor memU32 0x020e047c = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3

#=============================================================================

# DDR Controller Registers

#=============================================================================

# Manufacturer: ISSI

# Device Part Number: IS43/46TR16256AL

# Clock Freq.: 400MHz

# Density per CS in Gb: 8

# Chip Selects used: 1

# Number of Banks: 8

# Row address:     15

# Column address: 10

# Data bus width 32

#=============================================================================

#=============================================================================

# Calibration setup.

#=============================================================================

monitor memU32 0x021b0800 = 0xA1390003 # DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

# For target board, may need to run write leveling calibration to fine tune these settings.

monitor memU32 0x021b080c  = 0x001F001F

monitor memU32 0x021b0810 = 0x001F001F

##Read DQS Gating calibration

monitor memU32 0x021b083c = 0x42190219 # MPDGCTRL0 PHY0

monitor memU32 0x021b0840 = 0x017B0177 # MPDGCTRL1 PHY0

#Read calibration

monitor memU32 0x021b0848 = 0x4B4D4E4D # MPRDDLCTL PHY0

#Write calibration                   

monitor memU32 0x021b0850 = 0x3F3E2D36 # MPWRDLCTL PHY0

#read data bit delay: (3 is the reccommended default value, although out of reset value is 0)

monitor memU32 0x021b081c = 0x33333333 # DDR_PHY_P0_MPREDQBY0DL3

monitor memU32 0x021b0820 = 0x33333333 # DDR_PHY_P0_MPREDQBY1DL3

monitor memU32 0x021b0824 = 0x33333333 # DDR_PHY_P0_MPREDQBY2DL3

monitor memU32 0x021b0828 = 0x33333333 # DDR_PHY_P0_MPREDQBY3DL3

# Complete calibration by forced measurement:                 

monitor memU32 0x021b08b8 = 0x00000800 # DDR_PHY_P0_MPMUR0, frc_msr

#=============================================================================

# Calibration setup end

#=============================================================================

#MMDC init:

monitor memU32 0x021b0004 = 0x0002002D # MMDC0_MDPDC

monitor memU32 0x021b0008 = 0x00333030 # MMDC0_MDOTC

monitor memU32 0x021b000c = 0x3F435313 # MMDC0_MDCFG0

monitor memU32 0x021b0010 = 0xB66D8B63 # MMDC0_MDCFG1

monitor memU32 0x021b0014 = 0x01FF00DB # MMDC0_MDCFG2

#MDMISC: RALAT kept to the high level of 5.

#MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:

#a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3

#b. Small performence improvment

monitor memU32 0x021b0018 = 0x00001740 # MMDC0_MDMISC

monitor memU32 0x021b001c = 0x00008000 MMDC0_MDSCR, set the Configuration request bit during MMDC set up

monitor memU32 0x021b002c = 0x000026D2 # MMDC0_MDRWD

monitor memU32 0x021b0030 = 0x00431023 # MMDC0_MDOR

monitor memU32 0x021b0040 = 0x00000017 # Chan0 CS0_END

monitor memU32 0x021b0000 = 0x83190000 # MMDC0_MDCTL

#Mode register writes               

monitor memU32 0x021b001c = 0x04008032 # MMDC0_MDSCR, MR2 write, CS0

monitor memU32 0x021b001c = 0x00008033 # MMDC0_MDSCR, MR3 write, CS0

monitor memU32 0x021b001c = 0x00048031 # MMDC0_MDSCR, MR1 write, CS0

monitor memU32 0x021b001c = 0x05208030 # MMDC0_MDSCR, MR0write, CS0

monitor memU32 0x021b001c = 0x04008040 # MMDC0_MDSCR, ZQ calibration command sent to device on CS0

monitor memU32 0x021b0020 = 0x00005800 # MMDC0_MDREF

monitor memU32 0x021b0818 = 0x00011117 # DDR_PHY_P0_MPODTCTRL

monitor memU32 0x021b0004 = 0x0002556D # MMDC0_MDPDC now SDCTL power down enabled

monitor memU32 0x021b0404 = 0x00011006 # MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.

monitor memU32 0x021b001c = 0x00000000 # MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)

#=============================================================================

# Calibration setup end

#=============================================================================

monitor memU32 0x020e0010 = 0xF00000CF # enable AXI cache for VDOA/VPU/IPU

monitor memU32 0x020e0018 = 0x007F007F # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7

monitor memU32 0x020e001c = 0x007F007F # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7


load u-boot

cont

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davidziv
Contributor II

OK, found the right configuration for running U-BOOT from RAM

target remote localhost:2331

#monitor endian little

#monitor device MCIMX6S5

#monitor speed auto

monitor reset

monitor halt

monitor sleep 1000

#=============================================================================

# Disable WDOG

#=============================================================================

monitor memU32 0x020bc000 = 0x30

#=============================================================================

# Enable all clocks (they are disabled by ROM code)

#=============================================================================

monitor memU32 0x020c4068 = 0x00C03F3F

monitor memU32 0x020c406c = 0x0030FC03

monitor memU32 0x020c4070 = 0x0FFFC000

monitor memU32 0x020c4074 = 0x3FF00000

monitor memU32 0x020c4078 = 0x00FFF300

monitor memU32 0x020c407c = 0x0F0000C3

monitor memU32 0x020c4080 = 0x000003FF

#GPU and VPU not needed for boot

#monitor memU32 0x020c4084 = 0xffffffff

#=============================================================================

# IOMUX

#=============================================================================

#DDR IO TYPE:

monitor memU32 0x020e0774 = 0x000C0000 # IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE

monitor memU32 0x020e0754 = 0x00000000 # IOMUXC_SW_PAD_CTL_GRP_DDRPKE

#CLOCK:

monitor memU32 0x020e04ac = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0

monitor memU32 0x020e04b0 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1

#ADDRESS:

monitor memU32 0x020e0464 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS

monitor memU32 0x020e0490 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS

monitor memU32 0x020e074c = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_ADDDS

#Control:

monitor memU32 0x020e0494 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET

monitor memU32 0x020e04a0 = 0x00000000 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS

monitor memU32 0x020e04b4 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0

monitor memU32 0x020e04b8 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1

monitor memU32 0x020e076c = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_CTLDS

#Data Strobes:

monitor memU32 0x020e0750 = 0x00020000 # IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL

monitor memU32 0x020e04bc = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0

monitor memU32 0x020e04c0 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1

monitor memU32 0x020e04c4 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2

monitor memU32 0x020e04c8 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3

#Data:

monitor memU32 0x020e0760 = 0x00020000 # IOMUXC_SW_PAD_CTL_GRP_DDRMODE

monitor memU32 0x020e0764 = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B0DS

monitor memU32 0x020e0770 = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B1DS

monitor memU32 0x020e0778 = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B2DS

monitor memU32 0x020e077c = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B3DS

monitor memU32 0x020e0470 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0

monitor memU32 0x020e0474 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1

monitor memU32 0x020e0478 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2

monitor memU32 0x020e047c = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3

#=============================================================================

# DDR Controller Registers

#=============================================================================

# Manufacturer: ISSI

# Device Part Number: IS43/46TR16256AL

# Clock Freq.: 400MHz

# Density per CS in Gb: 8

# Chip Selects used: 1

# Number of Banks: 8

# Row address:     15

# Column address: 10

# Data bus width 32

#=============================================================================

#=============================================================================

# Calibration setup.

#=============================================================================

monitor memU32 0x021b0800 = 0xA1390003 # DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

# For target board, may need to run write leveling calibration to fine tune these settings.

monitor memU32 0x021b080c  = 0x001F001F

monitor memU32 0x021b0810 = 0x001F001F

##Read DQS Gating calibration

monitor memU32 0x021b083c = 0x42190219 # MPDGCTRL0 PHY0

monitor memU32 0x021b0840 = 0x017B0177 # MPDGCTRL1 PHY0

#Read calibration

monitor memU32 0x021b0848 = 0x4B4D4E4D # MPRDDLCTL PHY0

#Write calibration                   

monitor memU32 0x021b0850 = 0x3F3E2D36 # MPWRDLCTL PHY0

#read data bit delay: (3 is the reccommended default value, although out of reset value is 0)

monitor memU32 0x021b081c = 0x33333333 # DDR_PHY_P0_MPREDQBY0DL3

monitor memU32 0x021b0820 = 0x33333333 # DDR_PHY_P0_MPREDQBY1DL3

monitor memU32 0x021b0824 = 0x33333333 # DDR_PHY_P0_MPREDQBY2DL3

monitor memU32 0x021b0828 = 0x33333333 # DDR_PHY_P0_MPREDQBY3DL3

# Complete calibration by forced measurement:                 

monitor memU32 0x021b08b8 = 0x00000800 # DDR_PHY_P0_MPMUR0, frc_msr

#=============================================================================

# Calibration setup end

#=============================================================================

#MMDC init:

monitor memU32 0x021b0004 = 0x0002002D # MMDC0_MDPDC

monitor memU32 0x021b0008 = 0x00333030 # MMDC0_MDOTC

monitor memU32 0x021b000c = 0x3F435313 # MMDC0_MDCFG0

monitor memU32 0x021b0010 = 0xB66D8B63 # MMDC0_MDCFG1

monitor memU32 0x021b0014 = 0x01FF00DB # MMDC0_MDCFG2

#MDMISC: RALAT kept to the high level of 5.

#MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:

#a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3

#b. Small performence improvment

monitor memU32 0x021b0018 = 0x00001740 # MMDC0_MDMISC

monitor memU32 0x021b001c = 0x00008000 MMDC0_MDSCR, set the Configuration request bit during MMDC set up

monitor memU32 0x021b002c = 0x000026D2 # MMDC0_MDRWD

monitor memU32 0x021b0030 = 0x00431023 # MMDC0_MDOR

monitor memU32 0x021b0040 = 0x00000017 # Chan0 CS0_END

monitor memU32 0x021b0000 = 0x83190000 # MMDC0_MDCTL

#Mode register writes               

monitor memU32 0x021b001c = 0x04008032 # MMDC0_MDSCR, MR2 write, CS0

monitor memU32 0x021b001c = 0x00008033 # MMDC0_MDSCR, MR3 write, CS0

monitor memU32 0x021b001c = 0x00048031 # MMDC0_MDSCR, MR1 write, CS0

monitor memU32 0x021b001c = 0x05208030 # MMDC0_MDSCR, MR0write, CS0

monitor memU32 0x021b001c = 0x04008040 # MMDC0_MDSCR, ZQ calibration command sent to device on CS0

monitor memU32 0x021b0020 = 0x00005800 # MMDC0_MDREF

monitor memU32 0x021b0818 = 0x00011117 # DDR_PHY_P0_MPODTCTRL

monitor memU32 0x021b0004 = 0x0002556D # MMDC0_MDPDC now SDCTL power down enabled

monitor memU32 0x021b0404 = 0x00011006 # MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.

monitor memU32 0x021b001c = 0x00000000 # MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)

#=============================================================================

# Calibration setup end

#=============================================================================

monitor memU32 0x020e0010 = 0xF00000CF # enable AXI cache for VDOA/VPU/IPU

monitor memU32 0x020e0018 = 0x007F007F # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7

monitor memU32 0x020e001c = 0x007F007F # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7


load u-boot

cont

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igorpadykov
NXP Employee
NXP Employee

Hi David

one can look at

https://community.freescale.com/thread/376786

http://forum.segger.com/index.php?page=Thread&threadID=1550

http://forum.segger.com/index.php?page=Thread&threadID=1995

some jtag init scripts can be found in /tools folder of

"MX6_PLATFORM_SDK "

https://community.freescale.com/docs/DOC-94139

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

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davidziv
Contributor II

I have used this script to initialize IMX6

target remote localhost:2331

#monitor endian little

#monitor device MCIMX6S5

#monitor speed auto

monitor reset

monitor halt

monitor sleep 1000

#=============================================================================

# Disable WDOG

#=============================================================================

monitor memU32 0x020bc000 = 0x30

#=============================================================================

# Enable all clocks (they are disabled by ROM code)

#=============================================================================

monitor memU32 0x020c4068 = 0xffffffff

monitor memU32 0x020c406c = 0xffffffff

monitor memU32 0x020c4070 = 0xffffffff

monitor memU32 0x020c4074 = 0xffffffff

monitor memU32 0x020c4078 = 0xffffffff

monitor memU32 0x020c407c = 0xffffffff

monitor memU32 0x020c4080 = 0xffffffff

monitor memU32 0x020c4084 = 0xffffffff

#=============================================================================

# IOMUX

#=============================================================================

#DDR IO TYPE:

monitor memU32 0x020e0774 = 0x000C0000 # IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE

monitor memU32 0x020e0754 = 0x00000000 # IOMUXC_SW_PAD_CTL_GRP_DDRPKE

#CLOCK:

monitor memU32 0x020e04ac = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0

monitor memU32 0x020e04b0 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1

#ADDRESS:

monitor memU32 0x020e0464 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS

monitor memU32 0x020e0490 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS

monitor memU32 0x020e074c = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_ADDDS

#Control:

monitor memU32 0x020e0494 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET

monitor memU32 0x020e04a0 = 0x00000000 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS

monitor memU32 0x020e04b4 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0

monitor memU32 0x020e04b8 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1

monitor memU32 0x020e076c = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_CTLDS

#Data Strobes:

monitor memU32 0x020e0750 = 0x00020000 # IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL

monitor memU32 0x020e04bc = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0

monitor memU32 0x020e04c0 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1

monitor memU32 0x020e04c4 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2

monitor memU32 0x020e04c8 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3

#Data:

monitor memU32 0x020e0760 = 0x00020000 # IOMUXC_SW_PAD_CTL_GRP_DDRMODE

monitor memU32 0x020e0764 = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B0DS

monitor memU32 0x020e0770 = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B1DS

monitor memU32 0x020e0778 = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B2DS

monitor memU32 0x020e077c = 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B3DS

monitor memU32 0x020e0470 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0

monitor memU32 0x020e0474 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1

monitor memU32 0x020e0478 = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2

monitor memU32 0x020e047c = 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3

#=============================================================================

# DDR Controller Registers

#=============================================================================

# Manufacturer: ISSI

# Device Part Number: IS43/46TR16256AL

# Clock Freq.: 400MHz

# Density per CS in Gb: 8

# Chip Selects used: 1

# Number of Banks: 8

# Row address:     15

# Column address: 10

# Data bus width 32

#=============================================================================

#=============================================================================

# Calibration setup.

#=============================================================================

monitor memU32 0x021b0800 = 0xA1390003 # DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

# For target board, may need to run write leveling calibration to fine tune these settings.

monitor memU32 0x021b080c  = 0x0045004B

monitor memU32 0x021b0810 = 0x00240027

##Read DQS Gating calibration

monitor memU32 0x021b083c = 0x0238023C # MPDGCTRL0 PHY0

monitor memU32 0x021b0840 = 0x020C0214 # MPDGCTRL1 PHY0

#Read calibration

monitor memU32 0x021b0848 = 0x44464848 # MPRDDLCTL PHY0

#Write calibration                   

monitor memU32 0x021b0850 = 0x38342C32 # MPWRDLCTL PHY0

#read data bit delay: (3 is the reccommended default value, although out of reset value is 0)

monitor memU32 0x021b081c = 0x33333333 # DDR_PHY_P0_MPREDQBY0DL3

monitor memU32 0x021b0820 = 0x33333333 # DDR_PHY_P0_MPREDQBY1DL3

monitor memU32 0x021b0824 = 0x33333333 # DDR_PHY_P0_MPREDQBY2DL3

monitor memU32 0x021b0828 = 0x33333333 # DDR_PHY_P0_MPREDQBY3DL3

# Complete calibration by forced measurement:                 

monitor memU32 0x021b08b8 = 0x00000800 # DDR_PHY_P0_MPMUR0, frc_msr

#=============================================================================

# Calibration setup end

#=============================================================================

#MMDC init:

monitor memU32 0x021b0004 = 0x0002002D # MMDC0_MDPDC

monitor memU32 0x021b0008 = 0x00333040 # MMDC0_MDOTC

monitor memU32 0x021b000c = 0x676B52F3 # MMDC0_MDCFG0

monitor memU32 0x021b0010 = 0xB66D8B63 # MMDC0_MDCFG1

monitor memU32 0x021b0014 = 0x01FF00DB # MMDC0_MDCFG2

#MDMISC: RALAT kept to the high level of 5.

#MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:

#a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3

#b. Small performence improvment

monitor memU32 0x021b0018 = 0x00011740 # MMDC0_MDMISC

monitor memU32 0x021b001c = 0x00008000 MMDC0_MDSCR, set the Configuration request bit during MMDC set up

monitor memU32 0x021b002c = 0x000026D2 # MMDC0_MDRWD

monitor memU32 0x021b0030 = 0x006B1023 # MMDC0_MDOR

monitor memU32 0x021b0040 = 0x0000001F # Chan0 CS0_END

monitor memU32 0x021b0000 = 0x84190000 # MMDC0_MDCTL

#Mode register writes               

monitor memU32 0x021b001c = 0x02008032 # MMDC0_MDSCR, MR2 write, CS0

monitor memU32 0x021b001c = 0x00008033 # MMDC0_MDSCR, MR3 write, CS0

monitor memU32 0x021b001c = 0x00048031 # MMDC0_MDSCR, MR1 write, CS0

monitor memU32 0x021b001c = 0x05208030 # MMDC0_MDSCR, MR0write, CS0

monitor memU32 0x021b001c = 0x04008040 # MMDC0_MDSCR, ZQ calibration command sent to device on CS0

monitor memU32 0x021b0020 = 0x00007800 # MMDC0_MDREF

monitor memU32 0x021b0818 = 0x00022227 # DDR_PHY_P0_MPODTCTRL

monitor memU32 0x021b0004 = 0x0002556D # MMDC0_MDPDC now SDCTL power down enabled

monitor memU32 0x021b0404 = 0x00011006 # MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.

monitor memU32 0x021b001c = 0x00000000 # MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)

#UART PORT INIT

monitor memU32 0x020e0050 = 3 #

monitor memU32 0x020e004c = 3 #

monitor memU32 0x020308fc = 3 #

--------------------------------------------------------

Then I load the uboot

load u-boot

For some reason it doesn't start

BR

David.

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