How to enter the i.MX7D into LowPower IDLE on ITRON

[minoru_nishimura]

Dear all,

We run ITRON on i.MX7D.
We want to enter the i.MX7D into LowPower IDLE.
We refer to Chapter 5 Clocks and Power Management on i.MX7Dual
Application Processor Reference Manual.

Are the settings before entering LowPower IDLE correct for the following items?
・GPC
・CCM
・PMU
・WFI

The setting program of GPC is described below.

/****************************************************************/
/* Name : WaitLPMSetting
/* Fanction : General Power Controller(GPC)①
/****************************************************************/
static void WaitLPMSetting(void)
{
// When there is a request to shift to Low Power Mode, set so that the operation status shown in Table 5-5 will be achieved.
// ・Set the low power mode that the system will enter on the next assertion of the dsm_request signal.

// Basic Low power control Register(A7) ※For details, refer to Reference Manual 5.5.10.1
// GPC_LPCR_A7_BSC[3-2] (LPM1) = 01：WAIT
// GPC_LPCR_A7_BSC[1-0] (LPM0) = 01：WAIT page/890/5203
// Low power controlRegister(M4) ※For details, refer to Reference Manual 5.5.10.3
GPC_LPCR_A7_BSC = 0x00000005;
//[30:28] : A7_CO/A7_C1/LPM wakeup from external INT
//[14] : CLOCK OFF during STOP mode
//[3:0] : STOP mode

// GPC_LPCR_M4[1-0](LPM0)=01： WAIT page 893/5203
// GPC_LPCR_M4[2](LPM0)=1： enable M4 virtual PGC power down
// GPC_LPCR_M4[3](LPM0)=1： enable M4 virtual PGC power up
// GPC_LPCR_M4[14](LPM0)=0： LPM時 M4 clock disabled
GPC_LPCR_M4 = 0x00003FFD;
//[31] : DSM ingore to check M4 low power state
//[1:0] : M4 LPM run mode

// Advanced Low power controlRegister(A7) ※For details, refer to Reference Manual 5.5.10.2
// GPC_LPCR_A7_AD[16](L2_PGE)=0：L2 cache RAM not Power down page/891/5203
// GPC_LPCR_A7_AD[11](EN_C1_PUP)=1 :Wakeup C1 ON
// GPC_LPCR_A7_AD[9](EN_C0_PUP)=1:Wakeup C0 ON
// GPC_LPCR_A7_AD[4](EN_PLAT_PDN)=1:LPM SCU&L2 Cache OFF
// GPC_LPCR_A7_AD[3](EN_C1_PDN)=1 :LPM C1 OFF
// GPC_LPCR_A7_AD[1](EN_C0_PDN)=1:LPM C0 OFF
GPC_LPCR_A7_AD = 0x00000F1F;

//[16] : 1(ALL_OFF mode); 0(L2 retention mode)
//[11]/[9]: A7_C0/A7_C1
//[4] : A7_SCU
//[3]/[1] : A7_C0/A7_C1

GPC_SLPCR = 0xE000FFA7;

//[31] : enable DSM
//[30] : eneable regulator bypass
//[5:3] : wait 64 ckil clock cycles
//[2] : enable PMIC standby
//[1] : enable OSC power down
//[0] : bypass PMIC ready handshake

reg32_write(GPC_IPS_BASE_ADDR + 0x808, (reg32_read(GPC_IPS_BASE_ADDR + 0x808) & 0xFFFFC0C0) | 0x0801); //GPC_PGC_nPDNSCR, n=0
// General Power Controller(GPC)
// i.MX 7Dual Applications Processor Reference Manual, Rev. 1, 01 / 2018
// 882 NXP Semiconductors
// set C0.ISO2SW = 8 ; C0.ISO = 1;

reg32_write(GPC_IPS_BASE_ADDR + 0x848, (reg32_read(GPC_IPS_BASE_ADDR + 0x848) & 0xFFFFC0C0) | 0x0801); //GPC_PGC_nPDNSCR, n=1
// set C1.ISO2SW = 8 ; C1.ISO = 1;

reg32_write(GPC_IPS_BASE_ADDR + 0x888, (reg32_read(GPC_IPS_BASE_ADDR + 0x888) & 0xFFFFC0C0) | 0x1001); //GPC_PGC_nPDNSCR, n=2
// set SCU.ISO2SW = 16 ; SCU.ISO = 1;
//Special PGC setting #B for A7_Cx/SCU power up in same slot(SCU should be always ON comparing to C0 / C1)

reg32_write(GPC_IPS_BASE_ADDR + 0x804, (reg32_read(GPC_IPS_BASE_ADDR + 0x804) & 0xFF800040) | 0x10 | (0x1f << 7)); //GPC_PGC_nPUPSCR, n=0
// set C0.SW = 0x10 ; C0.SW2ISO = 0x1f ;

reg32_write(GPC_IPS_BASE_ADDR + 0x844, (reg32_read(GPC_IPS_BASE_ADDR + 0x844) & 0xFF800040) | 0x10 | (0x1f << 7)); //GPC_PGC_nPUPSCR, n=1

// set C1.SW = 0x10 ; C1.SW2ISO = 0x1f ;
reg32_write(GPC_IPS_BASE_ADDR + 0x884, (reg32_read(GPC_IPS_BASE_ADDR + 0x884) & 0xFF800040) | 0x1 | (0x0f << 7)); //GPC_PGC_nPUPSCR, n=2
// set SCU.SW = 0x1 ; SCU.SW2ISO = 0x0f ;

reg32_write(GPC_IPS_BASE_ADDR + 0x800, (reg32_read(GPC_IPS_BASE_ADDR + 0x800) & 0xFFFFFFFE)| 0x00000001); //GPC_PGC_nCTRL, n=0
// enable A7_C0 PGC power down

reg32_write(GPC_IPS_BASE_ADDR + 0x840, (reg32_read(GPC_IPS_BASE_ADDR + 0x840) & 0xFFFFFFFE)| 0x00000001); //GPC_PGC_nCTRL, n=1
// enable A7_C1 PGC power down

reg32_write(GPC_IPS_BASE_ADDR + 0x880, (reg32_read(GPC_IPS_BASE_ADDR + 0x880) & 0xFFFFFFFE)| 0x00000001); //GPC_PGC_nCTRL, n=2
// enable A7_SCU PGC power down

reg32_write(GPC_IPS_BASE_ADDR + 0x890, (0x59 << 10) | 0x5B | (0x51 << 20)); //GPC_PGC_SCU_AUXSW
// change nL2retn/mempwr/dftram to meet SCU power up timing
//fastmix/megamix PGC

reg32_write(GPC_IPS_BASE_ADDR + 0xA00, (reg32_read(GPC_IPS_BASE_ADDR + 0xA00) & 0xFFFFFFFE) | 0x00000001); //GPC_PGC_nCTRL, n=8 //PGC for fastmix/megamix
// enable MIX PGC power down
}
/****************************************************************/
/* Name : PowerLPMSetting
/* Function : General Power Controller(GPC)②
/****************************************************************/
static void PowerLPMSetting(void)
{
// Power up/down acknowledgment signal selection
// ・Select the signal to confirm the end of power up/down by LPM
// ・It is recommended to select the signal assigned to the last operating Slot

// Provisional setting
// GPC_PGC_ACK_SEL_A7=0x0001_0004(pdn_ack:SCU, pup_ack:A7_C0)
// GPC_PGC_ACK_SEL_M4=0x0001_0008(pdn_ack;MF, pup_ack:M4)
GPC_PGC_ACK_SEL_A7 = 0x00010004;
//[2] : A7_SCU PGC as LPM power down ack
//[16] : A7_C0 PGC as LPM power up ack
GPC_PGC_ACK_SEL_M4 = 0x00010008;
//[0] : M4 virtual PGC as M4 LPM power down ack
//[16] : M4 virtual PGC as M4 LPM power up ack
//GPC_MISC

//Provisional setting(A7：Fastmega,MIPI,OTG1,HSIC allocation、M4：Fastmega,MIPI,OTG1,HSIC allocation)
GPC_PGC_CPU_MAPPING = 0x00000505;
}

/****************************************************************/
/* Name : SlotSetting
/* Function : General Power Controller(GPC)③ Powre Up/Down Slot
/****************************************************************/
static void SlotSetting(void)
{
GPC_SLT0_CFG = 0x0006AA85; //GPC_SLTn_CFG, SLOT0
//[2]/[0] : A7_C0/A7_C1
//[4] : A7_SCU
//[6] : fastmix/megamix
//A7_Cx/SCU are power down in same slot. Special setting is required( see below PGC setting #A )
//[18] : M4 virtual PGC power down in SLOT0, same with fastmix/megamix PGC power down slot

GPC_SLT1_CFG = 0x00015570; //GPC_SLTn_CFG, SLOT1
//[7] : fastmix/megamix
//[19] : M4 virtual PGC power up in SLOT1, same with fastmix/megamix PGC power up slot

GPC_SLT2_CFG = 0x0008000A; //GPC_SLTn_CFG, SLOT2

GPC_SLT3_CFG = 0x00000000;
GPC_SLT4_CFG = 0x00000000;
GPC_SLT5_CFG = 0x00000000;
GPC_SLT6_CFG = 0x00000000;
GPC_SLT7_CFG = 0x00000000;
GPC_SLT8_CFG = 0x00000000;
GPC_SLT9_CFG = 0x00000000;
}

However, the current value does not drop to the desired value.
We want to stop all functions on Low Power IDLE.
Could you tell me the commands I need to enter before entering LowPower IDLE?

Best Regards,
Minoru