How to control gpio in uboot on ls1028

[Eddy1]

Hi:

I'm try to control GPIOs from U-boot. I found gpio control code from ../ls1028a/ls1028a.c  that used for reset PHY.Then , I try to add more MASK bit to control GPIO3_DAT01 and GPIO1_DAT27 and enable GPIO3 and GPIO1 on RCW.

On RCW:

add EC1_SAI3_6_PMUX=1 and IIC4_PMUX=1 

On uboot in board/freescale/ls1028a/ls1028a.c

#define GPIO2_BASE_ADDR 0x2320000
#define GPIO0_BASE_ADDR 0x2300000

static void ls1028ardb_reset_phy(void)
{
unsigned int val,val1,rst,rst1;
struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
struct ccsr_gpio *pgpio1 = (void *)(GPIO0_BASE_ADDR);
rst = (1<<30);
rst1 = (1<<4);

setbits_be32(&pgpio->gpdir, rst);
setbits_be32(&pgpio1->gpdir, rst1);
val = in_be32(&pgpio->gpdat);
val1 = in_be32(&pgpio1->gpdat);
setbits_be32(&pgpio->gpdat, val | rst);
mdelay(10);
setbits_be32(&pgpio1->gpdat, val1 | rst1);
mdelay(50);

printf("phy reset test\n");
}

But when measuring with a multimeter, it is found that the level is not high, and the level has not changed. Could you help solve this problem?

[ufedor]

Please provide U-Boot booting log (to check RCW) and outputs of the following commands:

"md.l 2300000 8"

"md.l 2320000 8"

[Eddy1]

Hi:

Attach uboot's log:

NOTICE: 2 GB DDR4, 32-bit, CL=11, ECC on
NOTICE: BL2: v1.5(release):efdac73-dirty
NOTICE: BL2: Built : 16:14:08, Jun 19 2021
NOTICE: BL31: v1.5(release):efdac73-dirty
NOTICE: BL31: Built : 16:14:08, Jun 19 2021
NOTICE: Welcome to LS1028 BL31 Phase

U-Boot 2020.04 (Jun 19 2021 - 16:13:03 +0800)

SoC: LS1028A Rev1.0 (0x870b0110)
Clock Configuration:
CPU0(A72):1500 MHz CPU1(A72):1500 MHz
Bus: 400 MHz DDR: 1600 MT/s
Reset Configuration Word (RCW):
00000000: 3c004010 00000030 00000000 00000000
00000010: 00000000 018f0000 0030c000 00000000
00000020: 020031a0 00002580 00000000 00000256
00000030: 00000000 00000010 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 100e7514 00000000
00000070: bb580000 00000000
Model: LS1028 Development Board
Board: LS1028, Version: 1.0, boot from SD
DRAM: 1.9 GiB
DDR 1.9 GiB (DDR4, 32-bit, CL=11, ECC on)
test3
gpio1=f0 gpio=0
phy reset test
Using SERDES1 Protocol: 47960 (0xbb58)
PCIe1: pcie@3400000 Root Complex: no link
PCIe2: pcie@3500000 Root Complex: no link
WDT: Started with servicing (60s timeout)
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... OK
EEPROM: Read failed.
In: serial
Out: serial
Err: serial
Net: phy init test2
phy init test3
ar8031 test
phy reset 10
reg：ffff phy_id:ffffffff
reg：ffff phy_id:ffffffff
reg：ffff phy_id:ffffffff
reg：ffff phy_id:ffffffff
reg：ffff phy_id:ffffffff
reg：ffff phy_id:ffffffff
Could not get PHY for emdio-3: addr 2

Warning: enetc-0 (eth0) using random MAC address - 26:f5:b5:ab:17:eb
eth0: enetc-0
Warning: enetc-2 (eth2) using random MAC address - a2:d3:f7:05:c0:c2
, eth2: enetc-2reg：670 phy_id:70670
reg：670 phy_id:70670
reg：670 phy_id:70670
reg：670 phy_id:70670
, eth4: swp0, eth5: swp1, eth6: swp2, eth7: swp3
Hit any key to stop autoboot: 0
=>
=>
=> md.l 2300000 8
02300000: 10000040 00000000 000000f0 000000f0 @...............
02300010: 00000000 00000000 ffffffff 00000000 ................
=> md.l 2320000 8
02320000: 40000040 00000000 70600000 70600000 @..@......`p..`p
02320010: 00000000 00000000 ffffffff 00000000 ................

=> mdio list
enetc-0:
emdio-3:
10 - Vitesse VSC8514 <--> swp0
11 - Vitesse VSC8514 <--> swp1
12 - Vitesse VSC8514 <--> swp2
13 - Vitesse VSC8514 <--> swp3
enetc-2:
felix-switch:

Then I can't read PHY ID (8033) directly. I don't know if it's caused by no reset?

[ufedor]

Please provide the processor connection schematics as pdf and explain in which points the gpio signals are probed.

[Eddy1]

Hi:

You can find the pin and PHY circuit in the attachment,In addition, the level of this pin can be controlled manually in uboot :gpio set 65  or gpio clear 65.I have marked my measurement points in the attachment.

Thanks!

[ufedor]

Please provide the processor connection schematics as PDF.

[Eddy1]

Hi:

I'm very sorry, at present I only have the schematic diagram of the base board, but it is designed according to NXP ls1028ardb, and the processor schematic diagram does not have CPLD (epm2210f256c5n).