How to control MIPI PHY power supply

[ko-hey]

Hi all

I want to know how to control MIPI PHY power. supply.

I'm using i.MX7D and have a custom board.

Q1.

How can I powered off the VDDA_PHY_1P8 ?

According to the P483 and 484 of RM, SW_PHY_1P8 seem to be able to power off.

Also the power rail of VDDA_1P8_IN has a switch in figure 5-9. (Please see the following blue circle I pointer out.) 

As a result, it must be have register to ON/OFF the VDDA_PHY_1P8.

Could you tell me which register can control the VDDA_PHY_1P8 ?

Q2

Is there any way to put CPU in Deep Sleep mode with keeping LP11 ?

Currently, if you set the CPU to Deep Sleep, the MIPI D - PHY lane will be fixed to 0V.

Q3

Also, can you maintain D-PHY LP11 with VDDA_MIPI_1P0 dropped?

I would like to put the MIPI D-PHY in the state of LP11 (MIPI standby) to the state of low power consumption on the CPU side.

Ko-hey

[igorpadykov]

Hi Ko-hey

>Q1.
please refer to i.MX7 RM sect.5.5.10.34 PU PGC software down trigger (GPC_PU_PGC_SW_PDN_REQ)
MIPI_PHY_SW_PDN_REQ - Software power down trigger for MIPI_PHY
http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf

>Q2.
unfortunately there no way to put CPU in Deep Sleep mode with keeping LP11.
According to i.MX7RM Table 5-5. Low Power Mode Definition MIPI is "OFF" except in
System IDLE mode. Also please check sect.4.1.1. Use case 1: Deep-Sleep Mode (DSM)
AN5383 i.MX 7DS Power Consumption Measurement

"All of the modules are disabled.
All analog PHYs are powered down."
http://cache.nxp.com/assets/documents/data/en/application-notes/AN5383.pdf

>Q3.
there is no way to maintain D-PHY LP11 with VDDA_MIPI dropped, as in LP11 state
D-PHY LP transmitter should mainatin output high level (typ.1.2V).

Best regards
igor
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