How do I specify the debug UART for the MIMX8ML8CVNKZAB?

[TK141]

Hello
I have finished designing a board featuring the MIMX8ML8CVNKZAB and two DDR4 (8GBit 512M x 16) buses. I am preparing to build the board and will soon receive the assembled board.

While preparing to check the communication between the SoC and the DDR, I came across the following comment in the mscale_ddr_tool_v3.31
MSCALE_DDR_Tool_User_Guide.pdf document:

1. Connect the target board to the PC host.

Connect a UART cable from the host computer to the MX8MSCALE debug UART.

Regarding the debug UART, this SoC has UART1 through UART4. Is there a designated port when using the debug UART? If so, do you know how to specify it?

[yipingwang]

Default debug UART on common i.MX8M Plus platforms

A53 uses uart2 as debug port and M7 uses uart4 as debug port.

You may choose any of the four UARTs (UART1–UART4) as the debug UART, as long as:

1. You routed that UART's TX/RX pins to a connector (or a USB‑serial IC), and
2. You configure:
• ATF (BL31 early output)
• U‑Boot stdout-path
• Linux Device Tree (chosen { stdout-path = &uartX; })

Please refer to the following link.

https://community.nxp.com/t5/NXP-Tech-Blog/How-to-Change-i-MX8MM-evk-Linux-Debug-UART/ba-p/1243938?a...

[TK141]

I apologize for the late reply. Thank you for your answer; it was very helpful.

I was able to establish a UART connection by specifying the Debug UART port in the i.MX8MP (865) DDR Controller Configuration Spreadsheet (MX8M_Plus_DDR4_RPA_v10.xlsx).

I referred to the following link for MX8M_Plus_DDR4_RPA_v10.xlsx:

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8MPlus-m865S-DDR-Register-Programmi...