How do I do use the VPU on OS other than Linux or Android?

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How do I do use the VPU on OS other than Linux or Android?

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忍松本
Contributor I

We are running on i.MX6Q the T-Kernel.
Order to use the VPU, we are porting the driver from Linux, but the problem has occurred.
This timing, is CPU crashes and no response.

--- vpu_lib.c L.443 ---
BitIssueCommand(NULL, FIRMWARE_GET);
-----------------------

Additional Information (Nov.22.2013):

  - i.MX6Q have four cores, but we are using only a single core.

  - Our environment

      imx-lib version : imx-lib-12.09.01

      board : Collage-MX6Q (Sohwa & Sophia Technologies)

Thanks in Advance.

Shinobu MATSUMOTO

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HongzhangYang
NXP Employee
NXP Employee

Daisuke,

Simple task like vpu_DecRegisterFrameBuffer() ends up very quickly, because VPU doesn't have much to do. I have no idea why it's slow in your env. You can keep printing PC(0x18) in busy loop to track where it takes VPU time.

0x10 means roll back happened. You need to call vpu_DecGetInitialInfo() again after you fill more bitstream. You'd better fill as much bistream as possible (or even complete clip) to simplify your bringing up.

BR

Hongzhang

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HongzhangYang
NXP Employee
NXP Employee

Daisuke,

Please check how many bytes were in bs buffer before each vpu_GetInitialInfo(). vpu_GetInitialInfo() should fail until complete sequence header was in buffer.

Regarding performance issue, please check Lily's commets above.

BR

Hongzhang

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daisuketsuchiya
Contributor II

Hello Hongzhang Yang,

I'm trying to display the video decoded by VPU using IPU.

Is it possible to output the frame data of RGB565 format from VPU?

And do you know which modules do the rotation and resizing of video in Linux environment?  I think it does not done in at least VPU, however could you tell me how to do rotation and resizing of output images by VPU?

Thank you.

Daisuke TSUCHIYA

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HongzhangYang
NXP Employee
NXP Employee

Daisuke,

VPU can only output I420 or NV12.

IPU can do rotation and resize. You can use v4l APIs to display by IPU.

VPU unit test displays VPU output with v4l API. You can run ./mxc_vpu_test.out to verify it and refer to display.c/dec.c for coding.

BR

Hongzhang

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eaglezhou
NXP Employee
NXP Employee

Hi, Daisuke

    I feel confusion about your test result.

    In general, vpu will always write yuv output into the memory space registered through vpu_DecRegisterFrameBuffer().

    otherwise, it will lead to illegal memory access.

    I think there must be somewhere wrong in your calling stack.

    vpu_DecRegisterFrameBuffer can only be called once for the same playback. e.g you can't change the frame buffer address dynamically.

    (1) first playback

         init -> open(handled 1) -> seqinit -> register frame (handle 1) -> decode/output -> ... -> decode/output -> close -> uninit.

    (2) second playback

         init -> open(handled 2) -> seqinit -> register frame (handle 2) -> decode/output -> ... -> decode/output -> close -> uninit.

Eagle

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daisuketsuchiya
Contributor II

Hello Hongzhang Yang,

A problem occurs when I play video repeatedly.

A decoded YUV data is not output to the address specified by vpu_DecRegisterFrameBuffer function after the second and subsequent of the video playback.

I was confirmed below by the memory dump.
YUV data of second time playback has been output to the address of the frame buffer which set by the vpu_DecRegisterFrameBuffer function at the first time playback.


eg.
1st time:

    I set as a frame buffer 0x1000.
    YUV data is output to the 0x1000.

2nd time:

    I set as a frame buffer 0x2000.
    YUV data is output to the 0x1000.

Is it possible to change the address of the frame buffer in the playback of the second and subsequent?
If possible, could you tell me how to change?

Best Regards,

Daisuke TSUCHIYA

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lily_zhang
NXP Employee
NXP Employee

Hello, Disuke-San:

Please refer to the following codes under http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu.c?h=imx_3.0.3... for relative register configurations:

/* enable AXI cache for VDOA/VPU/IPU

* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7

* clear OCRAM_CTL bits to disable pipeline control

*/

reg = __raw_readl(IOMUXC_GPR3);

reg &= ~IOMUXC_GPR3_OCRAM_CTL_EN;

__raw_writel(reg, IOMUXC_GPR3);

reg = __raw_readl(IOMUXC_GPR4);

reg |= IOMUXC_GPR4_VDOA_CACHE_EN | IOMUXC_GPR4_VPU_CACHE_EN |

IOMUXC_GPR4_IPU_CACHE_EN;

__raw_writel(reg, IOMUXC_GPR4);

__raw_writel(IOMUXC_GPR6_IPU1_QOS, IOMUXC_GPR6);

__raw_writel(IOMUXC_GPR7_IPU2_QOS, IOMUXC_GPR7);

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daisuketsuchiya
Contributor II

Hello Xiaoli Zhang-san,

Thank you for information.

I will confirm it.  By the way, I understood that this setting is in order to improve performance, and not mandatory.  Is this right?


Best Regards,

Daisuke TSUCHIYA

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lily_zhang
NXP Employee
NXP Employee

Yes. But recommend you to setup these 3 registers same with Linux side.

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karina_valencia
NXP Apps Support
NXP Apps Support

jackmao can you help on this case?

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