How can i trigger a software reset from u-boot WITHOUT using watchdog timer?

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How can i trigger a software reset from u-boot WITHOUT using watchdog timer?

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aasheesh
Contributor I

Please let me know how to trigger a software reset from u-boot without using watchdog timer.

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igorpadykov
NXP Employee
NXP Employee

Hi aasheesh

one can use WCR_SRS bit : writing to &wdog->wcr  in

u-boot/imx_watchdog.c at master · mripard/u-boot · GitHub

WDOGx_WCR, SRS - Software Reset Signal,

sect.70.7.1 Watchdog Control Register (WDOGx_WCR) IMX6DQRM

Best regards

igor

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igorpadykov
NXP Employee
NXP Employee

Hi aasheesh

one can use WCR_SRS bit : writing to &wdog->wcr  in

u-boot/imx_watchdog.c at master · mripard/u-boot · GitHub

WDOGx_WCR, SRS - Software Reset Signal,

sect.70.7.1 Watchdog Control Register (WDOGx_WCR) IMX6DQRM

Best regards

igor

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Note: If this post answers your question, please click the Correct Answer button. Thank you!

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aasheesh
Contributor I

Thank you for your prompt reply.But in my board the watchdog is not connected to the PMIC. So,even if i set the WCR_SRS bit,i think it will not do a reset.Is there any alternative method which does not use watchdog like maybe SRC register or something like that.

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igorpadykov
NXP Employee
NXP Employee

WCR_SRS will reset processor without usage of PMIC.

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aasheesh
Contributor I

Thank you.By deasserting the SRS bit,my reset works.However,I must first disable warm_reset_enable bit in SRC_SCR register.The problem in my board was that WDOG_B was not connected to PMIC,so a watchdog timeout will not reset the PMIC. I have made an observation.Please let me know whether i am correct.I think deasserting the SRS bit creates a warm reset but as my warm_reset_enable bit is disabled,all warm reset sources must generate a cold reset.Hence my warm reset is actually creating a cold reset.Is it correct?Thank you for your assistance. Looking forward for your reply.

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igorpadykov
NXP Employee
NXP Employee

I think your understanding is right.

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