How can I generate Interlaced video on HDMI port in i.MX8QM board

[mallibeerala]

Dear NXP Team,

I want to test Interlaced video output on HDMI port in i.MX8QM board, How can I generate Interlaced video on HDMI port.

Thanks & Regards,
Mallikarjuna

[Sanket_Parekh]

Hello Customer,

I hope you are doing well.

->The TV-in source plugin gets video frames from the TV decoder. It is based on the V4l2 capture interface. A command line example is as follows:
gst-launch-1.0 v4l2src ! autovideosink

The TV decoder is ADV7180. It supports NTSC and PAL TV modes. The output video frame is interlaced, so the sink plugin needs to enable deinterlacing. The default value of v4l2sink deinterlace is True.

->Please refer to this doc for more details.
https://www.nxp.com/docs/en/user-guide/IMX_LINUX_USERS_GUIDE.pdf

I hope this information helps!

Thanks & Regards,

[mallibeerala]

Hai Sanket,

I want to generate Interlaced video(with out giving external input) on HDMI port in i.MX8QM board.

Ex: While loading rootfs penguin images will display, I want these penguin images in interlaced video format.

Thanks & Regards,
Mallikarjuna

[Sanket_Parekh]

Hello @mallibeerala ,

I hope you are doing well.

I want to generate Interlaced video(without giving external input) on an HDMI port in i.MX8QM board.

->Please make sure to configure the HDMI port on 8qm, its device tree configurations.
I have shared an example for reference.

hdmi: hdmi@120000 {
        reg = <0x00120000 0x9000>;
        interrupts = <0 115 0x04>;
        gpr = <&gpr>;
        clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
                 <&clks IMX6QDL_CLK_HDMI_ISFR>;
        clock-names = "iahb", "isfr";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                hdmi_mux_0: endpoint {
                    remote-endpoint = <&ipu1_di0_hdmi>;
                };
            };

            port@1 {
                reg = <1>;

                hdmi_mux_1: endpoint {
                    remote-endpoint = <&ipu1_di1_hdmi>;
                };
            };
        };
    };

The HD Display TX controller expects the interlaced timing format to comply with the specification defined in CEA-861-F.
The field information will be extracted from the input signal (hsync, vsync, and de) and will be propagated towards the framer (i.e. VB-ID field bit in DisplayPort).

Please refer to Section 15.5.2.2.1.2.3 Fields to select interlace control and more details into RM.
https://www.nxp.com/webapp/Download?colCode=IMX8QMRM

I hope this helps you!

Thanks & Regards,

Sanket Parekh

[mallibeerala]

Hi Sanket,

I am configuring hdmi node as per below in "imx8qm-ss-hdmi.dtb", for interlaced output where I have to change below dts settings.

I am using kernel version 5.15.32

hdmi:hdmi@56268000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x56268000 0x1000>,
<0x56261000 0x1000>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <10>, <13>;
interrupt-names = "plug_in", "plug_out";
firmware-name = "hdmitxfw.bin";
status = "disabled";

clocks = <&clk IMX_SC_R_HDMI_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>,
<&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC2>,
<&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>,
<&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>,
<&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>,
<&hdmi_lpcg_phy 1>,
<&hdmi_lpcg_msi_hclk 0>,
<&hdmi_lpcg_pxl 0>,
<&hdmi_lpcg_phy 0>,
<&hdmi_lpcg_lis_ipg 0>,
<&hdmi_lpcg_apb 0>,
<&hdmi_lpcg_apb_mux_csr 0>,
<&hdmi_lpcg_apb_mux_ctrl 0>,
<&clk IMX_SC_R_HDMI_I2S IMX_SC_PM_CLK_BYPASS>,
<&hdmi_lpcg_i2s 0>;
clock-names = "dig_pll", "av_pll", "clk_ipg",
"clk_core", "clk_pxl", "clk_pxl_mux",
"clk_pxl_link", "lpcg_hdp", "lpcg_msi",
"lpcg_pxl", "lpcg_vif", "lpcg_lis",
"lpcg_apb", "lpcg_apb_csr", "lpcg_apb_ctrl",
"clk_i2s_bypass", "lpcg_i2s";
assigned-clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>,
<&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>,
<&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>;
assigned-clock-parents = <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>;
power-domains = <&pd IMX_SC_R_HDMI>,
<&pd IMX_SC_R_HDMI_PLL_0>,
<&pd IMX_SC_R_HDMI_PLL_1>;
power-domain-names = "hdmi", "pll0", "pll1";

port@0 {
reg = <0>;
hdmi_disp: endpoint {
remote-endpoint = <&dpu1_disp0_hdmi>;
};
};
};

Thanks & Regards,
Mallikarjuna