Hardware design to using boundary scan test of i.MX7

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Hardware design to using boundary scan test of i.MX7

ソリューションへジャンプ
1,522件の閲覧回数
toshiharu_shimi
Contributor I

Hi,
I use i.MX7 which is MCIMX7D3EVK10SD (12 x 12 mm) and I would like to use the Boundary scan test.
According to document "IMX7DSHDG" that mentioned as following.

toshiharu_shimi_0-1687333610809.png

So, My hardware design will supply to PCI PHY, but MCIMX7D3EVK10SD has no PCIE_VPTX pin.
(MCIMX7D5EVM10SD(19 x 19 mm) has PCIE_VP pin , PCIE_VPH pin and PCIE_VPTX pin.)
Should I design to power supply to  only PCIE_VP pin and PCIE_VPH pin?

 

ラベル(1)
0 件の賞賛
返信
1 解決策
1,435件の閲覧回数
joanxie
NXP TechSupport
NXP TechSupport

yes, correct, you can compare the difference between them

19x19

joanxie_1-1687672837502.png

 

12x12

joanxie_0-1687672806196.png

 

元の投稿で解決策を見る

0 件の賞賛
返信
6 返答(返信)
1,509件の閲覧回数
joanxie
NXP TechSupport
NXP TechSupport

what do you mean MCIMX7D3EVK10SD has no PCIE_VPTX pin? do you mind sharing your connection about PCIE_VP pin and PCIE_VPH pin?

0 件の賞賛
返信
1,495件の閲覧回数
toshiharu_shimi
Contributor I

Hi, @joanxie 
According to Data sheet IMX7DCEC.pdf, in table 99 "iMX7Dual 12x12mm supplies contact...",  there are PCIE_VP (AB13 Ball) and PCIE_VPH (Y15 Ball), but no PCIE_VP_TX.

toshiharu_shimi_0-1687392836933.png

On the other hand, table101 "iMX7Dual 19x19mm supplies contact...", There is PCIE_VP_TX (AA11 pins).

toshiharu_shimi_1-1687392903192.png

I use 12 x 12mm package. So that, I can not connect supply power to PCIE_VP_TX ball.

0 件の賞賛
返信
1,436件の閲覧回数
joanxie
NXP TechSupport
NXP TechSupport

yes, correct, you can compare the difference between them

19x19

joanxie_1-1687672837502.png

 

12x12

joanxie_0-1687672806196.png

 

0 件の賞賛
返信
1,357件の閲覧回数
toshiharu_shimi
Contributor I

Hi, @joanxie 

As per your reply, I  intend to power supply to PCIE_VP and PCIE_VPH for using Boundary Scan.

I don't use PCIe function, in that case, should other PCIe signals  (ex. PCIE_REXT)  are connected to floating or tie to grand?

Should I follow the "Table 5 Recommended connections for unused analog interfaces"  in "IMX7DCEC.pdf" excluding PCIE_VP and PCIE_VPH?

toshiharu_shimi_0-1688621591329.png

like below fig.?

toshiharu_shimi_1-1688622260639.png

 

 

0 件の賞賛
返信
1,336件の閲覧回数
joanxie
NXP TechSupport
NXP TechSupport

yes, if you don't use it, you can refer to the design guide

タグ(1)
0 件の賞賛
返信
991件の閲覧回数
toshiharu_shimi
Contributor I

I attempt to power supply to PCIE_VP and PCIE_VPH for using Boundary Scan.
Although I don't use PCIE, Current consumption is up 70mA.
I guess I use MIPI, so that current consumption of PCIE up too.
I set to disable PCIE_CTRL_CLK_ROOT and PCIE_PHY_CLK_ROOT of  LPCG. But it has no effect on current consumption. 
In that case, Are there other way to reduce the current consumption?

toshiharu_shimi_0-1702947649062.png

Would you teach me how to configure PCIe Full Powerdown mode?

toshiharu_shimi_0-1702971408168.png

 

 

0 件の賞賛
返信