HDMI interface on DI1

[tomasznowak]

Hello Community,

I'm involved in a project based on imx6Solo.

I would like to use LCD interface with DI0 and HDMI interface with DI1 of the IPU1.

In the file board-mx6q_sabresd.c I modifed hdmi_core_data.disp_id to 1 (it was 0 initially).

After booting the board over NFS

> setenv bootargs console=ttymxc2,115200 androidboot.console=ttymxc2 vmalloc=400M init=/init video=mxcfb0:dev=hdmi,1920x1080@60,bpp=32 video=mxcfb1:off video=mxcfb2:off fbmem=28M androidboot.hardware=freescale rw ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot}

the monitor complains that the signal is out of range/not valid.

On the other side, if hdmi_core_data.disp_id is set to 0, I can see Android booting nicely on the HDMI monitor...

Analyzing the log file show that the clock ipu1_di_clk_1 is enabled. What else do I have to set up to deliver proper clock/data signals from DI1?

Any help would be appreciated!

Tomasz

[Rita_Wang]

Hi Tomasz,

Would you tell us which board are you using?

Best Regards

Dan

[tomasznowak]

Hello Dan Wang,

I made my tests again using SabreSD reference board with an IMX6DL CPU.

As I mentioned before, the only thing I changed was the file arch/arm/march-mx6/board-mx6q_sabresd.c (hdmi_core_data.disp_id is set to 1 instead of 0).

I also added some debug code, i.e. in hdmi_init method to confirm that HDMI_MUX_CTL is properly set in the IOMUXC_GPR3 register).

Bootargs I used in both cases are taken from "Android Quick Start" document and look like this:

> setenv bootargs console=ttymxc0,115200 androidboot.console=ttymxc0 vmalloc=400M init=/init video=mxcfb0:dev=hdmi,1920x1080M@60,bpp=32 video=mxcfb1:off video=mxcfb2:off fbmem=28M androidboot.hardware=freescale

I attached log files for both cases. The only visible difference are warning messages:

imx-ipuv3 imx-ipuv3.0: IPU Warning - IPU_INT_STAT_10 = 0x00100000

imx-ipuv3 imx-ipuv3.0: IPU Warning - IPU_INT_STAT_5 = 0x00800000

Please let me know if you have any idea why the HDMI signal is correct when I use DI0 but inproper when using DI1.

According to the manual, it should work without any problem. What else do I have to enable (clocks etc)?

I measured also frequency of HDMI_CLK signal. In case of DI0 it's above 140Mhz, for DI1 it's around 64Mhz.

What part of the code is configuring the clock?

Thanks for the help

Tomasz

[jimmychan]

static struct ipuv3_fb_platform_data sabresd_fb_data[] = {

{ /*fb0*/

.disp_dev = "lcd",

.interface_pix_fmt = IPU_PIX_FMT_RGB565,

.mode_str = "CLAA-WVGA",

.default_bpp = 16,

.int_clk = true,

.late_init = false,

}, {

.disp_dev = "ldb",

.interface_pix_fmt = IPU_PIX_FMT_RGB666,

.mode_str = "LDB-XGA",

.default_bpp = 16,

.int_clk = false,

.late_init = false,

}, {

.disp_dev = "ldb",

.interface_pix_fmt = IPU_PIX_FMT_RGB666,

.mode_str = "LDB-XGA",

.default_bpp = 16,

.int_clk = false,

}, {

.disp_dev = "ldb",

.interface_pix_fmt = IPU_PIX_FMT_RGB666,

.mode_str = "LDB-VGA",

.default_bpp = 16,

.int_clk = false,

.late_init = false,

},

};

-- > LCD clock change to int_clk

If both of them are int_clk=false, then both clock will be came from PLL5. The confliction will be occurred.

The above example is that 'video0' set as LCD so it will use IPU internal clock to produce the pixel clock. Then HDMI will use the external PLL5 to produce the pixel clock.

[PKZ]

HI Jimmychan,

I am facing the similar issue with dual display (LVDS + HDMI).

Here is details of my configuration. The Hardware is designed based on SabreSD but the display is configured to use LVDS0 interface (SabreSD uses LVDS1). So far, using just single display (LVDS0), there is no issue, I modified the software configuration in the "fsl_mxc_ldb_platform_data" as below and was working fine.

static struct fsl_mxc_ldb_platform_data ldb_data = {

  .ipu_id = 0,

  .disp_id = 0,

  .ext_ref = 1,

  .mode = LDB_SIN0,

  .sec_ipu_id = 0,

  .sec_disp_id = 1,

};

The other configurations (i.e. hdmi and lcd configurations) remained the same as we were not using HDMI initially. Now, we need to have dual display. Thus, I started working on it. However, I am still very confused about the assigning the ipu IDs even after reading the posts in forum and the user manual.

1) Could you please clarify if the LVDS0 always uses the ipu_id 0 (i.e. IPU 1) and LVDS1 uses ipu_id 1 (IPU 2)? How about HDMI, can it be assigned to any ipu? what about the display id for HDMI?

2) As suggested by Tomasz, i have verified that the both ipu1_di_clk_0 and ipu1_di_clk_1 has the same parent clock, pll5_video_main_clk .

However, I donot see the HDMI clock when i measured the clock line. Is there any other register configuration I am missing?

Regards,

PK

[PKZ]

In addition, I am unable to view the Advance Display setting when HDMI cable is connected. It crashes when I try to go in!!

Thanks,

PK

[tomasznowak]

Hello PK,

what BSP version do you use? I'm using IMX6_JB422_110_ANDROID_SOURCE and from what I remember it doesn't have 'Advance Display' setting included anymore.

However you can test your 2nd monitor using Presentation class (http://developer.android.com/reference/android/app/Presentation.html).

An example application is included in Api Demos of the "Android SDK" (i.e. adt-bundle-windows-x86_64-20130917\sdk\samples\android-17\ApiDemos\src\com\example\android\apis\app\PresentationActivity.java)

Back to your problem, in my case the CONFIG_MX6_CLK_FOR_BOOTUI_TRANS was not defined preventing to set pll5_video_main_clk to be parent of ipu1_di_clk_1.

Please verify it.

Greetings

Tomasz

[tomasznowak · Accepted solution]

Hello jimmychan,

Finally I found the reason why the HDMI was not correct (when using DI1).

By default the method mx6_clocks_init (arch/arm/mach-mx6/clock.c) sets pll5_video_main_clk as the parent of the ipu1_di_clk_0.

When using DI1 we have to set pll5_video_main_clk as the parent clock of ipu1_di_clk_1!

Thanks for your help

Tomasz

[weidong_sun]

Hello, Tomsz,

     I have tested your requirments, please refer to the following steps:

(1)Adjust  fb data in SabreSD BSP

static struct ipuv3_fb_platform_data qcorein_fb_data[] = {

{

.disp_dev = "hdmi",

.interface_pix_fmt = IPU_PIX_FMT_RGB24,

.mode_str = "1920x1080M@60",

.default_bpp = 32,

.int_clk = false,

.late_init = false,

},

{

.disp_dev = "ldb",

.interface_pix_fmt = IPU_PIX_FMT_RGB666,

.mode_str = "LDB-WXGA",

.default_bpp = 16,

.int_clk = false,

.late_init = false,

},

};

(2) Adjust ipu and ipu id( Following codes for you as reference)

/* HDMI -- IPU1_DI0 */
static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
.ipu_id = 1,
.disp_id = 1,
};

/* RGB24 DISP0 LCD(Here is RGB24-->VGA via ADV7125 -- IPU0_DI0 */
static struct fsl_mxc_lcd_platform_data lcdif_data = {
.ipu_id = 0,
.disp_id = 0,
.default_ifmt = IPU_PIX_FMT_RGB24,
};

/* LVDS0 & LVDS1 use IPU0 DI0 & DI1, Now VGA can't be set High resolution */
static struct fsl_mxc_ldb_platform_data ldb_data = {
.ipu_id = 0,
.disp_id = 1,
.ext_ref = 1,
.mode = LDB_SEP1,
.sec_ipu_id = 0,
.sec_disp_id = 0,
};

(3)U-BOOT settings

baudrate=115200

netmask=255.255.255.0

loadaddr=0x10800000

rd_loadaddr=0x11000000

netdev=eth0

ethprime=FEC0

splashimage=0x30000000

splashpos=m,m

lvds_num=1

ethact=FEC0

bootdelay=15

gateway=192.168.1.1

ethaddr=00:04:9f:00:ea:d3

bootargs_base=setenv bootargs console=ttymxc0,115200

bootargs_android=setenv bootargs ${bootargs} init=/init androidboot.console=ttymxc0 androidboot.hardware=freescale

bootargs_nfs=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gateway}:${netmask}::eth0 off root=/dev/nfs nfsroot=${serverip}:${nfsroot}

bootcmd_net=run bootargs_base bootargs_android bootargs_nfs bootargs_disp;tftpboot ${loadaddr} uImage;bootm

nfsroot=/opt/nfsroot

bootargs_mmc=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gateway}:${netmask}::eth0 off

bootcmd_mmc=run bootargs_base bootargs_android bootargs_disp

bootargs_disp=setenv bootargs ${bootargs} video=mxcfb0:dev=hdmi,1920x1080M@60,bpp=32 video=mxcfb1:dev=lcd,1920x1080,bpp=32 video=mxcfb2:off fbmem=64M vmalloc=400M

ipaddr=192.168.1.110

bootargs=console=ttymxc0,115200 init=/init androidboot.console=ttymxc0 androidboot.hardware=freescale ip=192.168.1.110:192.168.1.103:192.168.1.1:255.255.255.0::eth0 off root=/dev/nfs nfsroot=192.168.1.103:/opt/nfsroot video=mxcfb0:dev=hdmi,1920x1080M@60,bpp=32 video=mxcfb1:dev=lcd,1920x1080,bpp=32 video=mxcfb2:off fbmem=64M vmalloc=400M

serverip=192.168.1.102

stdin=serial

stdout=serial

stderr=serial

fastboot_dev=mmc3

bootcmd=booti mmc3

HDMI can normally display !

[tomasznowak]

Hello Weidong Sun,

the Android BSP code in the version IMX6_JB422_110_ANDROID works out of the box with the HDMI, so no customization is required here.

By default HDMI is using DI0 of the IPU0 and it works for me with no problem when started with the following bootargs:

> setenv bootargs console=ttymxc0,115200 androidboot.console=ttymxc0 vmalloc=400M init=/init video=mxcfb0:dev=hdmi,1920x1080M@60,bpp=32 video=mxcfb1:off video=mxcfb2:off fbmem=28M androidboot.hardware=freescale

The problem is that it doesn't work if I try to use DI1 of the IPU0.

Please see my other post for more details.

Thank you for the help

Tomasz