HDMI PCLK 533MHz is not supported on your Linux running on i.mx8QM

[YukioOyama]

Hi all,

On a Linux system we are developing that runs on i.mx8qm, a 4k display with HDMI connection will not display.

Logs indicate that Pixel CLK is not supported.

[    7.161429] [drm] Started firmware!

[    7.179596] [drm] HDP FW Version - ver 34559 verlib 20560

[    7.201179] [drm] HDCP is disabled

[    7.249096] imx-drm display-subsystem: bound 56268000.hdmi (ops cdns_mhdp_imx_ops [cdns_mhdp_imx])

[    7.292834] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 1

[    7.360632] [drm] Mode: 3840x2160p533120

[    7.406561] [drm] Pixel clock: 533120 KHz, character clock: 666400, bpc is 10-bit.

[    7.406592] [drm] Pixel clk (533120 KHz) not supported, color depth (10-bit)

[    7.406598] [drm:cdns_hdmi_phy_set_imx8qm [cdns_mhdp_imx]] *ERROR* failed to set phy pclock

I think it is the same problem with this case.

https://community.nxp.com/t5/i-MX-Processors/HDMI-Pixel-clock-frequency-170000-kHz-is-not-supported/...

The EDID information is attached. (original data is binary but I am converting it to text data)

To solve this problem, do we just add the settings corresponding to the EDID to the imx8qm_ctrl_table[] below?

/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c

There are several other problems we have.
1, We cannot fully parse the EDID information
2, The parameters of this table are so complex that we do not understand what we should set
3, This display is one of our test objects. If we encounter the same problem with any of our customer's displays after the product is shipped, we will need to add the settings each time.

I need your help to add a new setting that is not in the table. And I also need a way to calculate that setting from the EDID information.

Best Regards,

Yukio Oyama

[YukioOyama]

Hello,

I have added the following to imx8qm_ctrl_table[].

{532000, 594000, 5000, 2970000, 2970000, 0x3C, 0x03, 0x06, 600, 0x24A, 0x00A, 0, 0, 0, 5940000, 5940000, 1, 1, 1, 2, 2, 0x01, 297000, 297000},
{532000, 594000, 6250, 3712500, 3712500, 0x3C, 0x03, 0x06, 375, 0x169, 0x00A, 0, 0, 0, 3712500, 3712500, 1, 1, 1, 2, 1, 0x00, 371250, 371250},
{532000, 594000, 7500, 4455000, 4455000, 0x3C, 0x03, 0x06, 450, 0x1B4, 0x00A, 0, 0, 0, 4455000, 4455000, 1, 1, 1, 2, 1, 0x00, 445500, 445500},
However, my display did not show. Are the parameters I set wrong?

I have not changed the PLL frequency to 533M frequency doubling. Is the PLL frequency the cause? I do not know where to change the PLL frequency.

The EDID information for my display is in the first question I posted.

These parameters are very difficult for me as I am not familiar with the displays. Please give me your help.

Best Regards,

Yukio Oyama

[YukioOyama]

Hi,b45499-san,

The EDID information for the display is attached in the first question. Is the table I have shown the correct target for modification and are there any additional modifications to be added?

I find it very difficult to get your table values from the EDID information. Please indicate the specific modifications to the table based on the EDID information.

Best Regards,

Yukio Oyama

[Rita_Wang]

Here when you add your screen in the imx8qm_ctrl_table[] you also Need to modify dts to change PLL frequency to 533M frequency doubling.

For the calculation table I will confirm it for you.

[YukioOyama]

Hi,

Thanks for your continued support!

Where is the change point to set the PLL frequency to 533 MHz?

The imx8qm_ctrl_table[] and PLL frequency, are these two places all that should be changed?

And please continue your follow up on the values that should be set.

BR,

Yukio Oyama

[Rita_Wang]

Yes, if your screen is not normal and do not see in the imx8qm_ctrl_table[], you need to add to it. And For the EDID information you need to contact your screen manufacturer.

[YukioOyama]

Is your support over? Do you have any additional support for me?
Yukio Oyama