HDMI DRM custom resolution and clock frequency

[simon6]

Hi,

I have been messing with a bunch of the kernel parameters for the iMX8MQ and I was curious as to how to generate values for the HDMI TX table in the kernel->drivers->GPU->DRM->iMX->HDP folder because I need a rather specific timing generated for a nonstandard HDMI input. I am looking to generate a PIX-CLK frequency of 204_800KHz.

(Note underscores are to keep track of decimal places and these are rewritten from impossible to read table data to something human-readable)

I guessed at a few values for the table as follows:

TABLE 8 Entry {
T8_PIXEL_CLK_FREQ_KHZ : 204_800,
T8_FEEDBACK_FACTOR : 1_000,
T8_DATA_RANGE_MBPS : 2_048_000,
T8_CMNDA_PLL0_IP_DIV : 0x03,
T8_CMN_REF_CLK_DIG_DIV : 0x01,
T8_REF_CLK_DIVIDER_SCALER : 0x01,
T8_PLL_FB_DIV_TOTAL : 220, ?
T8_CMNDA_PLL0_FB_DIV_LOW : 0x0AC,
T8_CMNDA_PLL0_FB_DIV_HIGH : 0x02C,
T8_PIXEL_DIV_TOTAL : 10,
T8_CMNDA_PLL0_PXDIV_LOW : 0x03,
T8_CMNDA_PLL0_PXDIV_HIGH : 0x03,
T8_VCO_FREQ_KHZ : 2_048_000,
T8_VCO_RING_SELECT : 0,
T8_CMNDA_HS_CLK_0_SEL : 1,
T8_CMNDA_HS_CLK_1_SEL : 1,
T8_HSCLK_DIV_AT_XCVR : 2,
T8_HSCLK_DIV_TX_SUB_RATE : 1,
T8_TX_CLK_KHZ : 1_024_000,
T8_CMNDA_PLL0_HS_SYM_DIV_SEL : 0x0,
T8_CMNDA_PLL0_CLK_FREQ_KHZ : 204_000,
T8_PIXEL_CLK_OUTPUT_ENABLE : 1,
T28HPC_HDMITX_CLOCK_CONTROL_TABLE_COLS_PIXEL_OUT
}

 &

TABLE9 Entry {
T9_VCO_FREQ_BIN : 25,
T9_PLL_VCO_FREQ_KHZ_MIN : 3060000,
T9_PLL_VCO_FREQ_KHZ_MAX : 3060000,
T9_VOLTAGE_TO_CURRENT_COARSE : 0x6,
T9_VOLTAGE_TO_CURRENT : 0x3,
T9_NDAC_CTRL : 0x1,
T9_PMOS_CTRL : 0x1,
T9_PTAT_NDAC_CTRL : 0x00,
T9_PLL_FEEDBACK_DIV_TOTAL : 0x07, ?
T9_CHARGE_PUMP_GAIN : 570,
T9_COARSE_CODE : 0x4C,
T9_V2I_CODE : 6,
T9_VCO_CAL_CODE : 225,
}

Any suggestions? Or is there a way I can talk with an application engineer?

I figured I'd give the forum a try before giving up on the iMX8 platform which we have spent several thousand on and move over to a platform that supports custom HDMI output readily.

Sincerely,

Simon

[scottbrust]

I managed to get a copy of the sheet. See attached. No idea if its still valid. My guess is that this is only relevant to the IMX8MQ since it references the 27 mhz reference clock instead of the 24mhz one used for the IMX8QM 

[eric_lee1]

The link is broken. Could you send me a copy of speadsheet please?

-Eric

[scottbrust]

I'm trying to troubleshoot support for an LCD screen and would like to see if this spreadsheet can help me add a custom timing. Can you share this file with me? (Im assuming its still relevant?)

[jacksong55]

Hi,

   I also has this issue when I need  to customize the non-standard HDMI resolution. Could you pls email me a  HDMI - pixel clock calculation tool.

Best regards!

Jackson

[weidong_sun · Accepted solution]

Hello Simon ,

Please see suggestions below, which comes from i.MX Expert.

----------------------------------------

The default BSP only supports standard HDMI clocks, but we can also add some more clocks.

It needs use HDMI - pixel clock calculation tools to generate the timing parameters.

you need calculate and fill the parameters in "Inputs" page of HDMI - pixel clock calculation.xlsx, if the parameters are avaliable, it will generate a new VCO item on t28hpc_hdmitx_pll_tuning_table_pixel_out.( drivers\gpu\drm\imx\hdp\API_AFE_t28hpc_hdmitx.c)

For example, assume pixel clock is 137.5Mhz.

{137520, 1000, 1374750, 0x03, 0x1, 0x1,  611, 0x1E5, 0x07A,  40, 0x012, 0x012, 5499000, 1, 2, 2, 2, 2,  687375, 0x2, 137475, 1},

------------------------------------------------------

I will send the tool to your email.

Hope above information is helpful for you.

Have a nice day!

B.R,

Weidong

[cotway]

@weidong_sun 

    Hi，Kernel version I use is 5.4.3 and only this version can be used。i get structure's parameter（struct hdmi_ctrl） by HDMI - pixel clock calculation.xlsx。but another structure's parameter(struct hdmi_pll_tuning) need add.

struct hdmi_ctrl {
u32 pixel_clk_freq_min;
u32 pixel_clk_freq_max;
u32 feedback_factor;
u32 data_range_kbps_min;
u32 data_range_kbps_max;
u32 cmnda_pll0_ip_div;
u32 cmn_ref_clk_dig_div;
u32 ref_clk_divider_scaler;
u32 pll_fb_div_total;
u32 cmnda_pll0_fb_div_low;
u32 cmnda_pll0_fb_div_high;
u32 pixel_div_total;
u32 cmnda_pll0_pxdiv_low;
u32 cmnda_pll0_pxdiv_high;
u32 vco_freq_min;
u32 vco_freq_max;
u32 vco_ring_select;
u32 cmnda_hs_clk_0_sel;
u32 cmnda_hs_clk_1_sel;
u32 hsclk_div_at_xcvr;
u32 hsclk_div_tx_sub_rate;
u32 cmnda_pll0_hs_sym_div_sel;
u32 cmnda_pll0_clk_freq_min;
u32 cmnda_pll0_clk_freq_max;
};

struct hdmi_pll_tuning {
u32 vco_freq_bin;
u32 vco_freq_min;
u32 vco_freq_max;
u32 volt_to_current_coarse;
u32 volt_to_current;
u32 ndac_ctrl;
u32 pmos_ctrl;
u32 ptat_ndac_ctrl;
u32 feedback_div_total;
u32 charge_pump_gain;
u32 coarse_code;
u32 v2i_code;
u32 vco_cal_code;
};

in file:drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c

i need hlp.

Best regards

[dernst]

I am also needing to support an LCD that has nonstandard timing requirements.

Could I also have a link to the tool?

BTW,  I was reviewing the mentioned c/h files (API_AFE_t28hpc_hdmitx.[ch]) and I do not see a table called t28hpc_hdmitx_pll_tuning_table_pixel_out.  Nor do I see entries similar to the one mentioned. 

I am guessing I may have a different version of source.  I pulled code from imx-android-10.0.0_2.5.0.zip.

[ttttttx]

I also faced this problem on the imx8mq-evk development board. I also need the  HDMI - pixel clock calculation tool , please send the tool to my email . Any guidance related to hdmi display is welcome.

Best wishes !

[et0]

Hi, the link for this tool is not working, please can it be shared again?

[jseo]

Hello, Weidong

Now I am using imx-8mq EVK.
I also need to set hdmi clock for custom resolution.

I searched here for the solution Finally, I found your answer here.
So, I would like to ask for HDMI - pixel clock calculation.

 Could you send the tool for me?

Thanks,
JM.

[zhanglei2015xx]

Would you pleae provide HDMI - pixel clock calculation  file?  The link has been invalid. Thanks.