Getting 8MMINILPD4-CPU2 design files working in OrCAD after downloading design file set

[rjm]

The design file set consists of a ZIP file with artwork data, a schematic (dsn), a board file (brd), two pdfs and a bom file.

After opening the schematic in capture, an opj file is created automatically.

The the following preparatory steps seems to be needed:

• add the Layout file by right clicking on "Layout" in the file list viewer (Add Layout)
• The layout can be opened by clicking on the layout which has been added now.

Yet, some other provisions must be carried out in order to get e.g. cross probing in operation, all of them operated from the PCB main menu:

• Update Schematic ... - Preview with report; then execute by clicking on Sync.
• It is then asked to regenerate netlist (via Tools menu). Result: Everywhere no physical part found for (PART).
• When I execute Update Layout, the Preview shows many Components removed and then added...
• After clicking on Sync, most of the errors are like these:

• ERROR(SPMHNI-189): Problems with the name of device 'XTAL_13Y_XTLOSC4_3P2X2P5MM_SM_IC_24MHZ': 'Name is too long.'.
  ERROR(SPMHNI-170): Device 'XTAL_13Y_XTLOSC4_3P2X2P5MM_SM_I' has library errors. Unable to transfer to Allegro.

I cannot get the setup such that I can operate conveniently. For sure, it has been verified that Intertool Communication (cross probing) has been enabled, but it does not work.

Hard to believe that it is related to failing libraries, because the schematic relies on the (internal) design cache.

I´d appreciate to receive appropriate hints.

[Yuri]

@rjm 
Hello,
 

    I cannot reproduce Your sequence under 17.4.
Have You tried it under 17.2?

Regards,
Yuri.

[Yuri]

@rjm 
Hello,

  What Allegro PCB designer release is used in the case?

Regards,
Yuri.

[rjm]

17.4 - the layout is loaded while the system reports that it is created using 17.2. And it would be saved in 17.4 format.

Precisely, OrCAD PCB Designer Professional's about screen says: 17.4-2019 S019 (7/8/2021). The splash screen says 2021.1.

OrCAD Capture CIS shows the same information (without the precise date marking).

[rjm]

@YuriRegardless whether you're having 17.2 or 17.4, I'd suggest that you apply the design file set as is downloadable by the user, and then see what happens. What I'm encountering is not limited to this i.MX8-related design file set only.

Currently, the ongoing project is stalled for this reason. I'd appreciate it to receive any appropriate hints quite soon.

Rob

PS: Yesterday I edited my reply to you in order to supply more detailed version information.

[Yuri]

@rjm 
Hello,

   please refer to the following:

https://community.nxp.com/t5/i-MX-Processors/8MMINI-BB-design-files-apparently-incomplete/m-p/128259...

Regards,
Yuri.

[rjm]

The reference seems to bee a clear indication that I have to help myself or consult OrCAD support (the link you supplied formerly was not of any help).

Rob

[Yuri]

@rjm 
Hello,

  I tried recommendations of the following OrCad help

http://referencedesigner.com/tutorials/allegro/allegro_page_38.php

 It is working in my case.

Regards,
Yuri.

[rjm · Accepted solution]

@Yuri 

It appears that the design parameter "Long name size" in PCB editor 17.4 is set to 31. As a consequence, updating the Netlist to Layout (using the new PCB->Design Sync of 17.4) fails because of numerous too long name errors.

And when syncing between layout and schematic fails (i.e. netlist error), then cross probing is not functional.

When the parameter is set to 255, syncing again (netlist update/import), then all is well.

More information is expected soon - a support case has been opened in parallel.

[rjm]

Here "more information" as announced:

Regarding the Long name size setting in PCB  editor, neither OrCAD support nor NXP support provide additional information whether the parameter setting of 31 after actually doing upref to 17.4 may appear to be a bug in 17.4 while the board file is updated from 17.2 to 17.4 format or whether the value is 31 when opened in 17.2 (question to NXP support - unanswered)

OrCAD support however gave the decisive hint to get net list generated correctly and hence: let cross probing operate correctly.

I'll mark the previous reply as "problem solved" and moreover, I have started a forum posting dedicated to Design Files issues: https://community.nxp.com/t5/i-MX-Processors/Portal-entry-for-OrCAD-Design-Files-issues/m-p/1350579

[rjm]

Thanks for your quick response. The point is: ITC is already enabled - by default. Hence I really don't know what is the cause of the problem. Then I read elsewhere that the netlist should be created and imported into PCB designer. And here, errors occur, as I have described on Friday.