GPIO1 issue

[marekvysocky]

Hi,
 On i.MX6UL I cannot set CSI DATA 5 pin as a GPIO1 DATA19 output.

I set IOMUX, GPIO_GDIR:
  HW_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SET(IOMUXC_BASE, 0x05UL);
  HW_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_CLR(IOMUXC_BASE, 0x0AUL);

  HW_GPIO_GDIR_SET(GPIO1_BASE, (1u << 19));
  HW_GPIO_DR_SET(GPIO1_BASE, (1u << 19));
but it doesn't do anything. What is wrong ?

[igorpadykov]

Hi Marek

seems there is some confusion for mux options for CSI_DATA05 pad, available options are
described on sect.30.5.122 SW_MUX_CTL_PAD_CSI_DATA05 SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05) i.MX6UL Reference Manual
http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6ULRM.pdf

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[marekvysocky]

Dear Igor.

You are my salvation. Thank you again. Problem (chaos) is in iMX6UL_registers.h file Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc. All rights reserved. This file is part of IAR Embedded Workbench.

Best regards

Marek